scholarly journals Reducing memory interference in multicore systems via application-aware memory channel partitioning

Author(s):  
Sai Prashanth Muralidhara ◽  
Lavanya Subramanian ◽  
Onur Mutlu ◽  
Mahmut Kandemir ◽  
Thomas Moscibroda
Author(s):  
Nizar Msadek

In modern Commercial Off-The-Shelf (COTS) multicore systems, cores can produce several simultaneous memory requests. The processing of such requests over the memory controller negatively impacts the interference delay triggered by running parallel tasks on the platform. In this paper, we propose a software-based testing approach for analyzing memory interference delay, when cores are exposed to extensive read/write requests that access in parallel their Cache Coherent Interconnect. The hardware targeted in this work is the well-known LayerScape QorIQ LS2085A, which can be approached as a potential successor to the Freescale QorIQ P4080. The test analysis was conducted based on a bare-metal operating system that we developed to guarantee a deterministic execution environment at all time points. Our testing was accomplished using a set of carefully designed synthetic benchmarks as well as TACLeBench benchmarks.


2006 ◽  
Author(s):  
Holly Dail ◽  
Graziano Obertelli ◽  
Francine Berman ◽  
Rich Wolski ◽  
Andrew Grimshaw
Keyword(s):  

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.


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