Telomere: Real-Time NAND Flash Storage

Modern solid-state disks achieve high data transfer rates due to their massive internal parallelism. However, out-of-place updates for flash memory incur garbage collection costs when valid data needs to be copied during space reclamation. The root cause of this extra cost is that solid-state disks are not always able to accurately determine data lifetime and group together data that expires before the space needs to be reclaimed. Real-time systems found in autonomous vehicles, industrial control systems, and assembly-line robots store data from hundreds of sensors and often have predictable data lifetimes. These systems require guaranteed high storage bandwidth for read and write operations by mission-critical real-time tasks. In this article, we depart from the traditional block device interface to guarantee the high throughput needed to process large volumes of data. Using data lifetime information from the application layer, our proposed real-time design, called Telomere , is able to intelligently lay out data in NAND flash memory and eliminate valid page copies during garbage collection. Telomere’s real-time admission control is able to guarantee tasks their required read and write operations within their periods. Under randomly generated tasksets containing 500 tasks, Telomere achieves 30% higher throughput with a 5% storage cost compared to pre-existing techniques.

Modeling of GIDL–Assisted Erase in 3–D NAND Flash Memory Arrays and Its Employment in NOR Flash–Based Spiking Neural Networks

Since the very first introduction of three-dimensional (3–D) vertical-channel (VC) NAND Flash memory arrays, gate-induced drain leakage (GIDL) current has been suggested as a solution to increase the string channel potential to trigger the erase operation. Thanks to that erase scheme, the memory array can be built directly on the top of a $$n^+$$ n + plate, without requiring any p-doped region to contact the string channel and therefore allowing to simplify the manufacturing process and increase the array integration density. For those reasons, the understanding of the physical phenomena occurring in the string when GIDL is triggered is important for the proper design of the cell structure and of the voltage waveforms adopted during erase. Even though a detailed comprehension of the GIDL phenomenology can be achieved by means of technology computer-aided design (TCAD) simulations, they are usually time and resource consuming, especially when realistic string structures with many word-lines (WLs) are considered. In this chapter, an analysis of the GIDL-assisted erase in 3–D VC nand memory arrays is presented. First, the evolution of the string potential and GIDL current during erase is investigated by means of TCAD simulations; then, a compact model able to reproduce both the string dynamics and the threshold voltage transients with reduced computational effort is presented. The developed compact model is proven to be a valuable tool for the optimization of the array performance during erase assisted by GIDL. Then, the idea of taking advantage of GIDL for the erase operation is exported to the context of spiking neural networks (SNNs) based on NOR Flash memory arrays, which require operational schemes that allow single-cell selectivity during both cell program and cell erase. To overcome the block erase typical of nor Flash memory arrays based on Fowler-Nordheim tunneling, a new erase scheme that triggers GIDL in the NOR Flash cell and exploits hot-hole injection (HHI) at its drain side to accomplish the erase operation is presented. Using that scheme, spike-timing dependent plasticity (STDP) is implemented in a mainstream NOR Flash array and array learning is successfully demonstrated in a prototype SNN. The achieved results represent an important step for the development of large-scale neuromorphic systems based on mature and reliable memory technologies.

Development of a Datalogger for Submarine Glider: Integration of Fault-Tolerant Software Layers

Submarine gliders are specialized systems used in applications such as environmental monitoring of marine fauna, in the oil industry, among others. The glider launch and capture is a costly process that requires substantial technological and human resources, so the orderly and error-free storage of data is of fundamental importance due to the subsequent analysis. The amount of information being obtained from the seabed is increasing, this leads to the need to develop robust and low-cost ad-hocsystems for this type of application. The challenge is the integration of the different software layers in the storage system because the monitored variables must be ordered according to different glider operations such as calibration data update and navigation. Additionally, to avoid data corruption in the memory chip, error control coding must be used. The goal of this paper is to present a novel design of different layers of software integrated into a datalogger: reception, error control, and storage logic for the different glider operations. The design of the datalogger is based on a NAND flash memory chip and an MSP430 microcontroller. To correct bit-flipping errors, a BCH code that corrects 4 errors for every 255 bits is implemented into the microcontroller. The design and evaluation are performed for different glider operations, and for different lengths and correction capabilities of the BCH module. A test to calculate the storage time has been carried out. This test shows that in the case of 256 bytes per sample, at 30 samples per minute, and 1 GB of storage capacity, it is possible to collect data from the glider sensors for 84 days. The results obtained show that our device is a useful option for storing underwater sensor data due to its real-time storage, power consumption, small size, easy integration, and its reliability, where the bit error rate BER is of 2.4 ×10−11.

Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory

In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability.

Machine Learning-Based Optimization Technique for High-Capacity V-NAND Flash Memory

In the NAND flash manufacturing process, thousands of internal electronic fuses (eFuse) should be tuned in order to optimize performance and validity. In this paper, we propose a machine learning-based optimization technique that can automatically tune the individual eFuse value based on a deep learning and genetic algorithm. Using state-of-the-art triple-level cell (TLC) V-NAND flash wafers, we trained our model and validated its effectiveness. The experimental results show that our technique can automatically optimize NAND flash memory, thus reducing total turnaround time (TAT) by 70 % compared with the manual-based process.