Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs

Proceedings of the 1997 international symposium on Physical design - ISPD '97 ◽

10.1145/267665.267703 ◽

1997 ◽

Author(s):

Juho Kim ◽

Cyrus Bamji ◽

Yanbin Jiang ◽

Sachin Sapatnekar

Keyword(s):

Buffer Insertion ◽

Transistor Sizing

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Interleaving buffer insertion and transistor sizing into a single optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.736136 ◽

1998 ◽

Vol 6 (4) ◽

pp. 625-633 ◽

Author(s):

Yanbin Jiang ◽

S.S. Sapatnekar ◽

C. Bamji ◽

Juho Kim

Keyword(s):

Buffer Insertion ◽

Transistor Sizing

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Combined transistor sizing with buffer insertion for timing optimization

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143) ◽

10.1109/cicc.1998.695051 ◽

2002 ◽

Author(s):

Yanbin Jiang ◽

S.S. Sapatnekar ◽

C. Bamji ◽

Juho Kim

Keyword(s):

Buffer Insertion ◽

Timing Optimization ◽

Transistor Sizing

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Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e94.a.2499 ◽

2011 ◽

Vol E94-A (12) ◽

pp. 2499-2509 ◽

Author(s):

Seidai TAKEDA ◽

Kyundong KIM ◽

Hiroshi NAKAMURA ◽

Kimiyoshi USAMI

Keyword(s):

Current Model ◽

Input Vector ◽

Delay Estimation ◽

Transistor Sizing ◽

Linear Current ◽

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Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption

2007 14th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2007.4511123 ◽

2007 ◽

Author(s):

Sherif A. Tawfik ◽

Volkan Kursun

Keyword(s):

Power Consumption ◽

Distribution Networks ◽

Transition Time ◽

Gradual Transition ◽

Clock Distribution ◽

Buffer Insertion ◽

Time Relaxation ◽

Clock Distribution Networks ◽

Reduced Power Consumption

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Sleep transistor sizing using timing criticality and temporal currents

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. ◽

10.1109/aspdac.2005.1466531 ◽

2005 ◽

Author(s):

A. Ramalingam ◽

Bin Zhang ◽

D.Z. Pan ◽

A. Devgan

Keyword(s):

Transistor Sizing

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A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing

10.1109/mlcad52597.2021.9531156 ◽

2021 ◽

Author(s):

Yaguang Li ◽

Yishuang Lin ◽

Meghna Madhusudan ◽

Arvind Sharma ◽

Sachin Sapatnekar ◽

...

Keyword(s):

Learning Approach ◽

Attention Network ◽

Transistor Sizing

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$O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2011.2174639 ◽

2012 ◽

Vol 31 (3) ◽

pp. 437-441 ◽

Author(s):

Zhuo Li ◽

Ying Zhou ◽

Weiping Shi

Keyword(s):

Time Algorithm ◽

Buffer Insertion

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Optimization of Custom MOS Circuits by Transistor Sizing

The Best of ICCAD ◽

10.1007/978-1-4615-0292-0_28 ◽

2003 ◽

pp. 347-364 ◽

Author(s):

Andrew R. Conn ◽

Paula K. Coulman ◽

Ruud A. Haring ◽

Gregory L. Morrill ◽

Chandu Visweswariah

Keyword(s):

Transistor Sizing ◽

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A Convex Programming Approach to Transistor Sizing

Design Automation for Timing-Driven Layout Synthesis ◽

10.1007/978-1-4615-3178-4_4 ◽

1993 ◽

pp. 113-140

Author(s):

Sachin S. Sapatnekar ◽

Sung-Mo Kang

Keyword(s):

Convex Programming ◽

Programming Approach ◽

Transistor Sizing

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Buffer Insertion Basics

Handbook of Algorithms for Physical Design Automation ◽

10.1201/9781420013481-26 ◽

2008 ◽

pp. 535-556

Author(s):

Jiang Hu ◽

Zhuo Li ◽

Shiyan Hu

Keyword(s):

Buffer Insertion

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