clock distribution networks Latest Research Papers

Decreasing the Power-Clock Resonant Signal Central Voltage as a Mean for Power Reduction in Integrated Power and Clock Distribution Networks

Indian Journal of Science and Technology ◽

10.17485/ijst/v14i33.1820 ◽

2021 ◽

Vol 14 (33) ◽

pp. 2671-2683

Author(s):

Seyed E Esmaeili ◽

◽

Abeer Imdoukh

Keyword(s):

Distribution Networks ◽

Power Reduction ◽

Clock Distribution ◽

Clock Distribution Networks

Using asynchronous clock distribution networks for timing SFQ circuits

Asynchronous Circuit Applications ◽

10.1049/pbcs061e_ch13 ◽

2019 ◽

pp. 269-292

Author(s):

Ramy N. Tadros ◽

Peter A. Beerel

Keyword(s):

Distribution Networks ◽

Clock Distribution ◽

Clock Distribution Networks

Slew and Skew Analysis for Low Power Clock Tree Synthesis Using Clock Distribution Networks

Sensor Letters ◽

10.1166/sl.2019.4123 ◽

2019 ◽

Vol 17 (8) ◽

pp. 641-653

Author(s):

R. Rajalakshmi ◽

S. M. Ramesh ◽

P. Sivakumar

Keyword(s):

Low Power ◽

Distribution Networks ◽

Clock Distribution ◽

Clock Tree ◽

Clock Distribution Networks ◽

Clock Tree Synthesis ◽

Tree Synthesis

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) ◽

10.1109/dtis.2019.8735052 ◽

2019 ◽

Author(s):

Thomas Lange ◽

Maximilien Glorieux ◽

Dan Alexandrescu ◽

Luca Sterpone

Keyword(s):

Failure Rate ◽

Distribution Networks ◽

Clock Distribution ◽

Single Event ◽

Functional Failure ◽

Clock Distribution Networks ◽

Single Event Transients

HCDN: Hybrid-Mode Clock Distribution Networks

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2018.2866224 ◽

2019 ◽

Vol 66 (1) ◽

pp. 251-262 ◽

Cited By ~ 1

Author(s):

Riadul Islam ◽

Matthew R. Guthaus

Keyword(s):

Distribution Networks ◽

Clock Distribution ◽

Hybrid Mode ◽

Clock Distribution Networks

Novel SET Mitigation Technique for Clock Distribution Networks

IEEE Transactions on Device and Materials Reliability ◽

10.1109/tdmr.2018.2802442 ◽

2018 ◽

Vol 18 (1) ◽

pp. 105-113 ◽

Cited By ~ 4

Author(s):

Peipei Hao ◽

Shuming Chen ◽

Pengcheng Huang ◽

Jianjun Chen ◽

Bin Liang

Keyword(s):

Distribution Networks ◽

Clock Distribution ◽

Clock Distribution Networks ◽

Mitigation Technique

Testing Clock Distribution Networks

2017 IEEE 26th Asian Test Symposium (ATS) ◽

10.1109/ats.2017.40 ◽

2017 ◽

Author(s):

Sying-Jyan Wang ◽

Hsiang-Hsueh Chen ◽

Chin-Hung Lien ◽

Katherine Shu-Min Li

Keyword(s):

Distribution Networks ◽

Clock Distribution ◽

Clock Distribution Networks

Voltage Scaled Clock Distribution Networks by using low swing D-flip-flop cell

10.22161/ijaers/nctet.2017.ece.18 ◽

2017 ◽

Author(s):

S.Zakia Sulthana ◽

N. Suguna

Keyword(s):

Distribution Networks ◽

Clock Distribution ◽

Flip Flop ◽

Clock Distribution Networks

Design Methodology for Voltage-Scaled Clock Distribution Networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2016.2539926 ◽

2016 ◽

Vol 24 (10) ◽

pp. 3080-3093 ◽

Cited By ~ 12

Author(s):

Can Sitik ◽

Weicheng Liu ◽

Baris Taskin ◽

Emre Salman

Keyword(s):

Design Methodology ◽

Distribution Networks ◽

Clock Distribution ◽

Clock Distribution Networks

Design of voltage scaled level converters in low power clock distribution networks

2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) ◽

10.1109/rteict.2016.7807888 ◽

2016 ◽

Author(s):

A. Rajesh ◽

B. L. Raju ◽

K. Chenna Kesava Reddy

Keyword(s):

Low Power ◽

Distribution Networks ◽

Clock Distribution ◽

Clock Distribution Networks

clock distribution networks
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

Decreasing the Power-Clock Resonant Signal Central Voltage as a Mean for Power Reduction in Integrated Power and Clock Distribution Networks

Using asynchronous clock distribution networks for timing SFQ circuits

Slew and Skew Analysis for Low Power Clock Tree Synthesis Using Clock Distribution Networks

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

HCDN: Hybrid-Mode Clock Distribution Networks

Novel SET Mitigation Technique for Clock Distribution Networks

Testing Clock Distribution Networks

Voltage Scaled Clock Distribution Networks by using low swing D-flip-flop cell

Design Methodology for Voltage-Scaled Clock Distribution Networks

Design of voltage scaled level converters in low power clock distribution networks

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clock distribution networksRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

Decreasing the Power-Clock Resonant Signal Central Voltage as a Mean for Power Reduction in Integrated Power and Clock Distribution Networks

Using asynchronous clock distribution networks for timing SFQ circuits

Slew and Skew Analysis for Low Power Clock Tree Synthesis Using Clock Distribution Networks

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

HCDN: Hybrid-Mode Clock Distribution Networks

Novel SET Mitigation Technique for Clock Distribution Networks

Testing Clock Distribution Networks

Voltage Scaled Clock Distribution Networks by using low swing D-flip-flop cell

Design Methodology for Voltage-Scaled Clock Distribution Networks

Design of voltage scaled level converters in low power clock distribution networks

clock distribution networks
Recently Published Documents