Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient

2016 ◽  
Vol 21 (4) ◽  
pp. 1-27
Author(s):  
Ramprasath S ◽  
Vinita Vasudevan
Keyword(s):  
Threshold Voltage ◽  
Efficient Algorithms ◽  
Gate Sizing ◽  
Discrete Gate Sizing

scholarly journals Sensitivity-guided metaheuristics for accurate discrete gate sizing

2012 ◽  
Author(s):  
Jin Hu ◽  
Andrew B. Kahng ◽  
SeokHyeong Kang ◽  
Myung-Chul Kim ◽  
Igor L. Markov
Keyword(s):  
Gate Sizing ◽  
Discrete Gate Sizing

A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment

2010 ◽  
Vol 29 (2) ◽  
pp. 223-234 ◽  
Author(s):  
Yifang Liu ◽  
Jiang Hu
Keyword(s):  
Threshold Voltage ◽  
Gate Sizing

Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing

2013 ◽  
Author(s):  
Vinicius S. Livramento ◽  
Chrystian Guth ◽  
Jose Luis Guntzel ◽  
Marcelo O. Johann
Keyword(s):  
Lagrangian Relaxation ◽  
Gate Sizing ◽  
Discrete Gate Sizing

scholarly journals Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage Assignment

Technologies ◽  
2021 ◽  
Vol 9 (4) ◽  
pp. 92
Author(s):  
Dimitrios Mangiras ◽  
Giorgos Dimitrakopoulos
Keyword(s):  
Lagrangian Relaxation ◽  
Threshold Voltage ◽  
Operating Conditions ◽  
Design Flow ◽  
Gate Sizing ◽  
Timing Closure ◽  
Last Mile ◽  
Placement And Routing ◽  
Routing Congestion ◽  
Timing Violations

Timing closure remains one of the most critical challenges of a physical synthesis flow, especially when the design operates under multiple operating conditions. Even if timing is almost closed at the end of the flow, last-mile placement and routing congestion optimizations may introduce new timing violations. Correcting such violations needs minimally disruptive techniques such as threshold voltage reassignment and gate sizing that affect only marginally the placement and routing of the almost finalized design. To this end, we transform a powerful Lagrangian-relaxation-based optimizer, used for global timing optimization early in the design flow, into a practical incremental timing optimizer that corrects small timing violations with fast runtime and without increasing the area/power of the design. The proposed approach was applied to already optimized designs of the ISPD 2013 benchmarks assuming that they experience new timing violations due to local wire rerouting. Experimental results show that in single corner designs, timing is improved by more than 36% on average, using 45% less runtime. Correspondingly, in a multicorner context, timing is improved by 39% when compared to the fully-fledged version of the timing optimizer.

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