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Sensitivity-guided metaheuristics for accurate discrete gate sizing
Proceedings of the International Conference on Computer-Aided Design - ICCAD '12
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10.1145/2429384.2429428
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2012
◽
Cited By ~ 31
Author(s):
Jin Hu
◽
Andrew B. Kahng
◽
SeokHyeong Kang
◽
Myung-Chul Kim
◽
Igor L. Markov
Keyword(s):
Gate Sizing
◽
Discrete Gate Sizing
Download Full-text
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Cited By
References
Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm
2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
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10.1109/isvlsi.2019.00059
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2019
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Author(s):
Henrique Placido
◽
Ricardo Reis
Keyword(s):
Lagrangian Relaxation
◽
Gate Sizing
◽
Discrete Gate Sizing
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Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient
ACM Transactions on Design Automation of Electronic Systems
◽
10.1145/2896819
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2016
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Vol 21
(4)
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pp. 1-27
Author(s):
Ramprasath S
◽
Vinita Vasudevan
Keyword(s):
Threshold Voltage
◽
Efficient Algorithms
◽
Gate Sizing
◽
Discrete Gate Sizing
Download Full-text
Strongly NP-hard discrete gate sizing problems
Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93
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10.1109/iccd.1993.393332
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2002
◽
Cited By ~ 14
Author(s):
W.N. Li
Keyword(s):
Gate Sizing
◽
Np Hard
◽
Discrete Gate Sizing
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Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
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10.7873/date.2013.370
◽
2013
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Cited By ~ 8
Author(s):
Vinicius S. Livramento
◽
Chrystian Guth
◽
Jose Luis Guntzel
◽
Marcelo O. Johann
Keyword(s):
Lagrangian Relaxation
◽
Gate Sizing
◽
Discrete Gate Sizing
Download Full-text
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
◽
10.1007/s10878-009-9267-0
◽
2009
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Vol 21
(4)
◽
pp. 497-510
◽
Cited By ~ 1
Author(s):
Chen Liao
◽
Shiyan Hu
Keyword(s):
Approximation Scheme
◽
Gate Sizing
◽
Delay Minimization
◽
Discrete Gate Sizing
Download Full-text
A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation
ACM Transactions on Design Automation of Electronic Systems
◽
10.1145/2647956
◽
2014
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Vol 19
(4)
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pp. 1-25
◽
Cited By ~ 7
Author(s):
Vinicius S. Livramento
◽
Chrystian Guth
◽
José Luís Güntzel
◽
Marcelo O. Johann
Keyword(s):
Lagrangian Relaxation
◽
Gate Sizing
◽
Hybrid Technique
◽
Discrete Gate Sizing
Download Full-text
Evaluating the impact of slew on delay and power of neighboring gates in discrete gate sizing
2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS)
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10.1109/lascas.2012.6180359
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2012
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Cited By ~ 1
Author(s):
Vinicius dos S. Livramento
◽
Chrystian Guth
◽
Jose Luis Guntzel
◽
Marcelo O. Johann
Keyword(s):
Gate Sizing
◽
The Impact
◽
Discrete Gate Sizing
Download Full-text
Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment
2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)
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10.1109/mocast52088.2021.9493338
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2021
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Author(s):
Dimitrios Mangiras
◽
Giorgos Dimitrakopoulos
Keyword(s):
Lagrangian Relaxation
◽
Threshold Voltage
◽
Gate Sizing
◽
Discrete Gate Sizing
Download Full-text
Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model
Proceedings of the 25th edition on Great Lakes Symposium on VLSI - GLSVLSI '15
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10.1145/2742060.2742094
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2015
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Cited By ~ 1
Author(s):
Jiani Xie
◽
C.Y. Roger Chen
Keyword(s):
Lookup Table
◽
Gate Sizing
◽
Delay Model
◽
Delay Minimization
◽
Discrete Gate Sizing
Download Full-text
Timing yield optimization via discrete gate sizing using globally-informed delay PDFs
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
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10.1109/iccad.2010.5654205
◽
2010
◽
Author(s):
Shantanu Dutt
◽
Huan Ren
Keyword(s):
Gate Sizing
◽
Yield Optimization
◽
Discrete Gate Sizing
Download Full-text
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