Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 ◽

10.7873/date.2013.370 ◽

2013 ◽

Author(s):

Vinicius S. Livramento ◽

Chrystian Guth ◽

Jose Luis Guntzel ◽

Marcelo O. Johann

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Discrete Gate Sizing

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Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi.2019.00059 ◽

2019 ◽

Author(s):

Henrique Placido ◽

Ricardo Reis

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Discrete Gate Sizing

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A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2647956 ◽

2014 ◽

Vol 19 (4) ◽

pp. 1-25 ◽

Author(s):

Vinicius S. Livramento ◽

Chrystian Guth ◽

José Luís Güntzel ◽

Marcelo O. Johann

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Hybrid Technique ◽

Discrete Gate Sizing

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Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment

2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST) ◽

10.1109/mocast52088.2021.9493338 ◽

2021 ◽

Author(s):

Dimitrios Mangiras ◽

Giorgos Dimitrakopoulos

Keyword(s):

Lagrangian Relaxation ◽

Threshold Voltage ◽

Gate Sizing ◽

Discrete Gate Sizing

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Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) ◽

10.1109/icecs.2012.6463706 ◽

2012 ◽

Author(s):

Vinicius dos S. Livramento ◽

Chrystian Guth ◽

Jose Luis Guntzel ◽

Marcelo O. Johann

Keyword(s):

Lagrangian Relaxation ◽

Leakage Power ◽

Gate Sizing ◽

Power Minimization ◽

Discrete Gate Sizing

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Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. ◽

10.1109/iccad.2004.1382535 ◽

2005 ◽

Author(s):

D. Sinha ◽

Hai Zhou

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Timing Constraints ◽

Crosstalk Reduction

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Sensitivity-guided metaheuristics for accurate discrete gate sizing

Proceedings of the International Conference on Computer-Aided Design - ICCAD '12 ◽

10.1145/2429384.2429428 ◽

2012 ◽

Author(s):

Jin Hu ◽

Andrew B. Kahng ◽

SeokHyeong Kang ◽

Myung-Chul Kim ◽

Igor L. Markov

Keyword(s):

Gate Sizing ◽

Discrete Gate Sizing

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Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2014.2305847 ◽

2014 ◽

Vol 33 (4) ◽

pp. 546-557 ◽

Author(s):

Guilherme Flach ◽

Tiago Reimann ◽

Gracieli Posser ◽

Marcelo Johann ◽

Ricardo Reis

Keyword(s):

Lagrangian Relaxation ◽

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Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2896819 ◽

2016 ◽

Vol 21 (4) ◽

pp. 1-27

Author(s):

Ramprasath S ◽

Vinita Vasudevan

Keyword(s):

Threshold Voltage ◽

Efficient Algorithms ◽

Gate Sizing ◽

Discrete Gate Sizing

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Fast Lagrangian Relaxation based gate sizing using multi-threading

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) ◽

10.1109/iccad.2015.7372601 ◽

2015 ◽

Author(s):

Ankur Sharma ◽

David Chinnery ◽

Sarvesh Bhardwaj ◽

Chris Chu

Keyword(s):

Lagrangian Relaxation ◽

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Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2019.2915324 ◽

2020 ◽

Vol 39 (7) ◽

pp. 1456-1469 ◽

Author(s):

Ankur Sharma ◽

David Chinnery ◽

Tiago Reimann ◽

Sarvesh Bhardwaj ◽

Chris Chu

Keyword(s):

Lagrangian Relaxation ◽

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