circuit optimization
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2022 ◽  
Vol 21 ◽  
pp. 10-17
Author(s):  
Alexander Zemliak

The design process for analogue circuit design is formulated on the basis of the optimum control theory. The artificially introduced special control vector is defined for the redistribution of computational costs between network analysis and parametric optimization. This redistribution minimizes computer time. The problem of the minimal-time network design can be formulated in this case as a classical problem of the optimal control for some functional minimization. There is a principal difference between the new approach and before elaborated methodology. This difference is based on a higher level of the problem generalization. In this case the structural basis of design strategies is more complete and this circumstance gives possibility to obtain a great value of computer time gain. Numerical results demonstrate the effectiveness and prospects of a more generalized approach to circuit optimization. This approach generalizes the design process and generates an infinite number of the different design strategies that will serve as the structural basis for the minimal time algorithm construction. This paper is advocated to electronic systems built with transistors. The main equations for the system design process were elaborated.


2021 ◽  
Author(s):  
Mousa Al-Qawasmi

A single tile in a mesh-based FPGA includes both the routing block and the logic block. The area estimate of a tile in an FPGA is used to determine the physical length of an FPGA’s routing segments. An estimate of the physical length of the routing segments is needed in order to accurately assess the performance of a proposed FPGA architecture. The VPR (Versatile Place and Route) and the COFFE (Circuit Optimization for FPGA Exploration) tools are widely used meshbased FPGA exploration environments. These tools map, place, and route benchmark circuits on FPGA architectures. Subsequently, based on area and delay measurements, the best architectural parameters of an FPGA are decided. The area models of the VPR and COFEE tools take only transistor size as input to estimate the area of a circuit. Realistically, the layout area of a circuit depends on both the transistor size and the number of metal layers that are available to route the circuit. This work measures the effect of the number of metal layers that are available for routing on FPGA layout area through a series of carefully laid out 4-LUTs (4-input Lookup Tables). Based on measured results, a correction factor for the COFFE area equation is determined. The correction factor is a function of both the transistor drive strength and the number of metal layers that are available for routing. Consequently, a new area estimation equation, that is based on the COFFE area model, is determined. The proposed area equation takes into consideration the effect of both the transistor drive strength and the number of metal layers that are available for routing on layout area. The area prediction error of the proposed area equation is significantly less than the area prediction errors of the VPR and COFFE area models.


2021 ◽  
Author(s):  
Mousa Al-Qawasmi

A single tile in a mesh-based FPGA includes both the routing block and the logic block. The area estimate of a tile in an FPGA is used to determine the physical length of an FPGA’s routing segments. An estimate of the physical length of the routing segments is needed in order to accurately assess the performance of a proposed FPGA architecture. The VPR (Versatile Place and Route) and the COFFE (Circuit Optimization for FPGA Exploration) tools are widely used meshbased FPGA exploration environments. These tools map, place, and route benchmark circuits on FPGA architectures. Subsequently, based on area and delay measurements, the best architectural parameters of an FPGA are decided. The area models of the VPR and COFEE tools take only transistor size as input to estimate the area of a circuit. Realistically, the layout area of a circuit depends on both the transistor size and the number of metal layers that are available to route the circuit. This work measures the effect of the number of metal layers that are available for routing on FPGA layout area through a series of carefully laid out 4-LUTs (4-input Lookup Tables). Based on measured results, a correction factor for the COFFE area equation is determined. The correction factor is a function of both the transistor drive strength and the number of metal layers that are available for routing. Consequently, a new area estimation equation, that is based on the COFFE area model, is determined. The proposed area equation takes into consideration the effect of both the transistor drive strength and the number of metal layers that are available for routing on layout area. The area prediction error of the proposed area equation is significantly less than the area prediction errors of the VPR and COFFE area models.


2021 ◽  
Vol 20 ◽  
pp. 362-371
Author(s):  
Alexander Zemliak

The minimization of the processor time of designing can be formulated as a problem of time minimization for transitional process of dynamic system. A special control vector that changes the internal structure of the equations of optimization procedure serves as a principal tool for searching the best strategies with the minimal CPU time. In this case a well-known maximum principle of Pontryagin is the best theoretical approach for finding of the optimum structure of control vector. Practical approach for realization of the maximum principle is based on the analysis of behavior of a Hamiltonian for various strategies of optimization. The possibility of applying the maximum principle to the problem of optimization of electronic circuits is analyzed. It is shown that in spite of the fact that the problem of optimization is formulated as a nonlinear task, and the maximum principle in this case isn't a sufficient condition for obtaining a minimum of the functional, it is possible to obtain the decision in the form of local minima. The relative acceleration of the CPU time for the best strategy found by means of maximum principle compared with the traditional approach is equal two to three orders of magnitude.


Quantum ◽  
2021 ◽  
Vol 5 ◽  
pp. 580
Author(s):  
Sergey Bravyi ◽  
Ruslan Shaydulin ◽  
Shaohan Hu ◽  
Dmitri Maslov

The Clifford group is a finite subgroup of the unitary group generated by the Hadamard, the CNOT, and the Phase gates. This group plays a prominent role in quantum error correction, randomized benchmarking protocols, and the study of entanglement. Here we consider the problem of finding a short quantum circuit implementing a given Clifford group element. Our methods aim to minimize the entangling gate count assuming all-to-all qubit connectivity. First, we consider circuit optimization based on template matching and design Clifford-specific templates that leverage the ability to factor out Pauli and SWAP gates. Second, we introduce a symbolic peephole optimization method. It works by projecting the full circuit onto a small subset of qubits and optimally recompiling the projected subcircuit via dynamic programming. CNOT gates coupling the chosen subset of qubits with the remaining qubits are expressed using symbolic Pauli gates. Software implementation of these methods finds circuits that are only 0.2% away from optimal for 6 qubits and reduces the two-qubit gate count in circuits with up to 64 qubits by 64.7% on average, compared with the Aaronson-Gottesman canonical form.


SPIN ◽  
2021 ◽  
Author(s):  
Mingyu Chen ◽  
Yu Zhang ◽  
Yongshang Li

In the NISQ era, quantum computers have insufficient qubits to support quantum error correction, which can only perform shallow quantum algorithms under noisy conditions. Aiming to improve the fidelity of quantum circuits, it is necessary to reduce the circuit depth as much as possible to mitigate the coherent noise. To address the issue, we propose PaF , a Pattern matching-based quantum circuit rewriting algorithm Framework to optimize quantum circuits. The algorithm framework finds all sub-circuits satisfied in the input quantum circuit according to the given external pattern description, then replaces them with better circuit implementations. To extend the capabilities of PaF , a general pattern description format is proposed to make rewriting patterns in existing work become machine-readable. In order to evaluate the effectiveness of PaF , we employ the BIGD benchmarks in QUEKO benchmark suite to test the performance and the result shows that PaF provides a maximal speedup of [Formula: see text] by using few patterns.


2021 ◽  
Author(s):  
Jiwoo Hong ◽  
Sunghoon Kim ◽  
Jaeha Kim ◽  
Dongsuk Jeon

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1209
Author(s):  
Yejin Ha ◽  
Hyungsoon Shin ◽  
Wookyung Sun ◽  
Jisun Park

A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM). Most studies on 1T-DRAM focus on device-level operation to replace 1T-1C-DRAM. To utilize 1T-DRAM as a memory device, we must understand its circuit-level operation, in addition to its device-level operation. Therefore, we studied the memory performance depending on device location in an array circuit and the circuit configuration by using the 1T-DRAM structure reported in the literature. The simulation results show various disturbances and their effects on memory performance. These disturbances occurred because the voltages applied to each device during circuit operation are different. We analyzed the voltage that should be applied to each voltage line in the circuit to minimize device disturbance and determine the optimized bias condition and circuit structure to achieve a large sensing margin and realize operation as a memory device. The results indicate that the memory performance improves when the circuit has a source line and the bias conditions of the devices differ depending on the write data at the selected device cell. Therefore, the sensing margin of the 1T-DRAM used herein can expectedly be improved by applying the proposed source line (SL) structure.


ACTA IMEKO ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 134
Author(s):  
Laszlo Kazup ◽  
Angela Varadine Szarka

<p class="Abstract">Contactless braking methods (with capability of energy recuperation) are more and more widely used and they replace the traditional abrasive and dissipative braking techniques. In case of rotating motion, the method is trivial and often used nowadays. But when the movement is linear and fast alternating, there are only a few possibilities to break the movement. The basic goal of research project is to develop a linear braking method based on the magnetic principle, which enables the efficient and highly controllable braking of alternating movements. Frequency of the alternating movement can be in wide range, aim of the research to develop contactless braking method for vibrating movement for as higher as possible frequency. The research includes examination and further development of possible magnetic implementations and existing methods, so that an efficient construction suitable for the effective linear movement control can be created. The first problem to be solved is design a well-constructed magnetic circuit with high air gap induction, which provides effective and good dynamic parameters for the braking devices. The present paper summarizes the magnetostatics design of “voice-coil linear actuator” type actuators and the effects of structure-related flux scattering and its compensation.</p>


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