discrete gate sizing Latest Research Papers

2021 ◽

Author(s):

Dimitrios Mangiras ◽

Giorgos Dimitrakopoulos

Keyword(s):

Lagrangian Relaxation ◽

Threshold Voltage ◽

Gate Sizing ◽

Discrete Gate Sizing

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Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi.2019.00059 ◽

2019 ◽

Author(s):

Henrique Placido ◽

Ricardo Reis

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Discrete Gate Sizing

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Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2896819 ◽

2016 ◽

Vol 21 (4) ◽

pp. 1-27

Author(s):

Ramprasath S ◽

Vinita Vasudevan

Keyword(s):

Threshold Voltage ◽

Efficient Algorithms ◽

Gate Sizing ◽

Discrete Gate Sizing

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Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model

Proceedings of the 25th edition on Great Lakes Symposium on VLSI - GLSVLSI '15 ◽

10.1145/2742060.2742094 ◽

2015 ◽

Cited By ~ 1

Author(s):

Jiani Xie ◽

C.Y. Roger Chen

Keyword(s):

Lookup Table ◽

Gate Sizing ◽

Delay Model ◽

Delay Minimization ◽

Discrete Gate Sizing

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A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2647956 ◽

2014 ◽

Vol 19 (4) ◽

pp. 1-25 ◽

Cited By ~ 7

Author(s):

Vinicius S. Livramento ◽

Chrystian Guth ◽

José Luís Güntzel ◽

Marcelo O. Johann

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Hybrid Technique ◽

Discrete Gate Sizing

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Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 ◽

10.7873/date.2013.370 ◽

2013 ◽

Cited By ~ 8

Author(s):

Vinicius S. Livramento ◽

Chrystian Guth ◽

Jose Luis Guntzel ◽

Marcelo O. Johann

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Discrete Gate Sizing

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Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) ◽

10.1109/icecs.2012.6463706 ◽

2012 ◽

Author(s):

Vinicius dos S. Livramento ◽

Chrystian Guth ◽

Jose Luis Guntzel ◽

Marcelo O. Johann

Keyword(s):

Lagrangian Relaxation ◽

Leakage Power ◽

Gate Sizing ◽

Power Minimization ◽

Discrete Gate Sizing

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Evaluating the impact of slew on delay and power of neighboring gates in discrete gate sizing

2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS) ◽

10.1109/lascas.2012.6180359 ◽

2012 ◽

Cited By ~ 1

Author(s):

Vinicius dos S. Livramento ◽

Chrystian Guth ◽

Jose Luis Guntzel ◽

Marcelo O. Johann

Keyword(s):

Gate Sizing ◽

The Impact ◽

Discrete Gate Sizing

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Sensitivity-guided metaheuristics for accurate discrete gate sizing

Proceedings of the International Conference on Computer-Aided Design - ICCAD '12 ◽

10.1145/2429384.2429428 ◽

2012 ◽

Cited By ~ 31

Author(s):

Jin Hu ◽

Andrew B. Kahng ◽

SeokHyeong Kang ◽

Myung-Chul Kim ◽

Igor L. Markov

Keyword(s):

Gate Sizing ◽

Discrete Gate Sizing

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Timing yield optimization via discrete gate sizing using globally-informed delay PDFs

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) ◽

10.1109/iccad.2010.5654205 ◽

2010 ◽

Author(s):

Shantanu Dutt ◽

Huan Ren

Keyword(s):

Gate Sizing ◽

Yield Optimization ◽

Discrete Gate Sizing

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discrete gate sizing
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment

Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient

Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing

Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization

Evaluating the impact of slew on delay and power of neighboring gates in discrete gate sizing

Sensitivity-guided metaheuristics for accurate discrete gate sizing

Timing yield optimization via discrete gate sizing using globally-informed delay PDFs

Export Citation Format

discrete gate sizingRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment

Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient

Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing

Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization

Evaluating the impact of slew on delay and power of neighboring gates in discrete gate sizing

Sensitivity-guided metaheuristics for accurate discrete gate sizing

Timing yield optimization via discrete gate sizing using globally-informed delay PDFs

discrete gate sizing
Recently Published Documents