Functional test generation for delay faults in combinational circuits

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/290833.290845 ◽

1998 ◽

Vol 3 (2) ◽

pp. 231-248 ◽

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Test Generation ◽

Functional Test ◽

Delay Faults ◽

Combinational Circuits

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Functional test generation for delay faults in combinational circuits

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.480204 ◽

2002 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

Functional Test ◽

Delay Faults ◽

Combinational Circuits

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NEST: a nonenumerative test generation method for path delay faults in combinational circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.476581 ◽

1995 ◽

Vol 14 (12) ◽

pp. 1505-1515 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy ◽

P. Uppaluri

Keyword(s):

Test Generation ◽

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

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An efficient automatic test generation system for path delay faults in combinational circuits

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512097 ◽

2002 ◽

Author(s):

A.K. Majhi ◽

J. Jacob ◽

L.M. Patnaik ◽

V.D. Agrawal

Keyword(s):

Test Generation ◽

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults ◽

Generation System ◽

Automatic Test Generation ◽

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Functional test generation for path delay faults

Proceedings of the Fourth Asian Test Symposium ◽

10.1109/ats.1995.485358 ◽

2002 ◽

Author(s):

M.K. Srinivas ◽

V.D. Agrawal ◽

M.L. Bushnell

Keyword(s):

Test Generation ◽

Functional Test ◽

Delay Faults ◽

Path Delay Faults

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Test generation for primitive path delay faults in combinational circuits

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97 ◽

10.1109/iccad.1997.643605 ◽

1997 ◽

Author(s):

Tekumalla ◽

Menon

Keyword(s):

Test Generation ◽

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

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Tests for small gate delay faults in combinational circuits and a test generation method

Systems and Computers in Japan ◽

10.1002/(sici)1520-684x(19970615)28:6<68::aid-scj8>3.0.co;2-k ◽

1997 ◽

Vol 28 (6) ◽

pp. 68-76

Author(s):

Hiroshi Takahashi ◽

Takashi Watanabe ◽

Toshiyuki Matsunaga ◽

Yuzo Takamatsu

Keyword(s):

Test Generation ◽

Delay Faults ◽

Combinational Circuits

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Hierarchical test generation for combinational circuits with real defects coverage

Microelectronics Reliability ◽

10.1016/s0026-2714(02)00080-x ◽

2002 ◽

Vol 42 (7) ◽

pp. 1141-1149 ◽

Author(s):

T Cibáková ◽

M Fischerová ◽

E Gramatová ◽

W Kuzmicz ◽

W.A Pleskacz ◽

...

Keyword(s):

Test Generation ◽

Combinational Circuits

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Functional test generation for FSMs by fault extraction

32nd Design Automation Conference ◽

10.1145/196244.196622 ◽

1994 ◽

Author(s):

Bapiraju Vinnakota ◽

Jason Andrews

Keyword(s):

Test Generation ◽

Functional Test

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A satisfiability-based test generator for path delay faults in combinational circuits

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545574 ◽

2005 ◽

Author(s):

Chih-Ang Chen ◽

S.K. Gupta

Keyword(s):

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

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An Automatic Test Generation Method for Crosstalk Delay Faults Using Modified FAN Algorithm

Test Generation of Crosstalk Delay Faults in VLSI Circuits ◽

10.1007/978-981-13-2493-2_4 ◽

2018 ◽

pp. 57-77

Author(s):

S. Jayanthy ◽

M. C. Bhuvaneswari

Keyword(s):

Test Generation ◽

Delay Faults ◽

Automatic Test Generation ◽

Automatic Test ◽

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