Statistical Gate-Delay Modeling with Copulas

The growing impact of process variations on circuit performance has become a major concern for deep-submicron integrated circuit design, resulting in numerous SSTA-algorithms. The acceptance of such algorithms in industry however will be dependent on modeling the real silicon behavior in SSTA. This includes that the statistical gate-delay models must consider arbitrary process variations and dependencies. In this paper, we introduce the innovative concept of Copulas to handle this topic. A complete Matlab based framework starting from process parameter statistics up to the computation of the statistical gate-delay distribution is presented. Experimental results demonstrate the importance of accounting realistic process variations.

New voltage and temperature scalable gate delay model applied to a 14nm technology

<p>The following work shows an innovative approach to model the timing of<br />standard cells. By using mathematical models instead of the classical SPICE-based characterization, a high amount of CPU (Central Processing Unit) cores is saved and less amount of data is stored. In the present work,<br />characterization of cells of a standard cell library is done in an hour whereas<br />it is done in 650 hours with the classical method. Also, a method for<br />validating and verification of the precision of the modelled data is presented<br />by comparing them on a implemented circuit. The output of implementations shows less than 3% of error between the two methods.</p>