The layout of a circuit can influence the probability of occurrence of faults. In this
paper, we develop algorithms that can take advantage of this fact to reduce the chances
of hard-to-detect (HTD) faults from occurring. We primarily focus on line bridge faults
in this paper. We define a bridge fault f as an HTD fault if an automatic test pattern
generator fails to generate a test vector for f in a reasonable amount of CPU-time. It is
common practice to drop such HTD faults from consideration during test generation.
The chip fault coverage achieved by a test set is poor if the fault set consists of many
HTD faults. We can combat this problem by avoiding altogether, or by reducing the
probability of, the occurrence of HTD faults. In this paper, we consider hard-to-detect
bridging faults and show how module placement rules can be derived to reduce the
probability of these faults. A genetic placement algorithm that optimizes area while
respecting these rules is presented. The placement algorithm has been implemented for
standard-cell layout style on a SUN/SPARC and tested against several sample circuits.
An efficient automatic test generation system for path delay faults in combinational circuits
