A performance analysis framework for exploiting GPU microarchitectural capability

Author(s):  
Keren Zhou ◽  
Guangming Tan ◽  
Xiuxia Zhang ◽  
Chaowei Wang ◽  
Ninghui Sun
Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1090
Author(s):  
Xiuli Yang ◽  
Yanhong Huang ◽  
Jianqi Shi ◽  
Zongyu Cao

With increasing demands of deterministic and real-time communication, network performance analysis is becoming an increasingly important research topic in safety-critical areas, such as aerospace, automotive electronics and so on. Time-triggered Ethernet (TTEthernet) is a novel hybrid network protocol based on the Ethernet standard; it is deterministic, synchronized and congestion-free. TTEthernet with a time-triggered mechanism meets the real-time and reliability requirements of safety-critical applications. Time-triggered (TT) messages perform strict periodic scheduling following the offline schedule tables. Different scheduling strategies have an effect on the performance of TTEthernet. In this paper, a performance analysis framework is designed to analyze the end-to-end delay, backlog bounds and resource utilization of network by real-time calculus. This method can be used as a base for the performance evaluation of TTEthernet scheduling. In addition, this study discusses the impacts of clock synchronization and traffic integration strategies on TT traffic in the network. Finally, a case study is presented to prove the feasibility of the performance analysis framework.


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