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Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip
ACM Transactions on Design Automation of Electronic Systems
◽
10.1145/3223046
◽
2018
◽
Vol 23
(5)
◽
pp. 1-25
◽
Cited By ~ 7
Author(s):
Dongjin Lee
◽
Sourav Das
◽
Janardhan Rao Doppa
◽
Partha Pratim Pande
◽
Krishnendu Chakrabarty
Keyword(s):
Energy Efficient
◽
Network On Chip
◽
3D Network
◽
On Chip
Download Full-text
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References
Energy efficient 3D network-on-chip based on approximate communication
Computer Networks
◽
10.1016/j.comnet.2021.108652
◽
2022
◽
Vol 203
◽
pp. 108652
Author(s):
M. Momeni
◽
H.S. Shahhoseini
Keyword(s):
Energy Efficient
◽
Network On Chip
◽
3D Network
◽
On Chip
◽
Approximate Communication
Download Full-text
Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithms
Proceedings of the 35th International Conference on Computer-Aided Design - ICCAD '16
◽
10.1145/2966986.2980096
◽
2016
◽
Cited By ~ 4
Author(s):
Sourav Das
◽
Janardhan Rao Doppa
◽
Partha Pratim Pande
◽
Krishnendu Chakrabarty
Keyword(s):
Energy Efficient
◽
Optimization Algorithms
◽
Network On Chip
◽
3D Network
◽
On Chip
Download Full-text
Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures
2010 IEEE Computer Society Annual Symposium on VLSI
◽
10.1109/isvlsi.2010.60
◽
2010
◽
Cited By ~ 2
Author(s):
Iasonas Filippopoulos
◽
Iraklis Anagnostopoulos
◽
Alexandros Bartzas
◽
Dimitrios Soudris
◽
George Economakos
Keyword(s):
Energy Efficient
◽
Network On Chip
◽
Systematic Exploration
◽
On Chip
◽
Application Specific
Download Full-text
ELBA-NoC: ensemble learning-based accelerator for 2D and 3D network-on-chip architectures
International Journal of Computational Science and Engineering
◽
10.1504/ijcse.2020.113176
◽
2020
◽
Vol 23
(4)
◽
pp. 319
Author(s):
Anil Kumar
◽
Basavaraj Talawar
Keyword(s):
Ensemble Learning
◽
Network On Chip
◽
3D Network
◽
On Chip
◽
2D And 3D
Download Full-text
Low Latency and Energy Efficient Optical Network-on-Chip Using Wavelength Assignment
IEEE Photonics Technology Letters
◽
10.1109/lpt.2012.2226939
◽
2012
◽
Vol 24
(24)
◽
pp. 2296-2299
◽
Cited By ~ 15
Author(s):
Zheng Chen
◽
Huaxi Gu
◽
Yintang Yang
◽
Ke Chen
Keyword(s):
Energy Efficient
◽
Optical Network
◽
Network On Chip
◽
Wavelength Assignment
◽
Low Latency
◽
On Chip
Download Full-text
Energy-Efficient Network-on-Chip Architectures for Multi-Core Systems
Handbook of Energy-Aware and Green Computing, Volume 1
◽
10.1201/b11643-7
◽
2012
◽
pp. 39-66
Keyword(s):
Energy Efficient
◽
Network On Chip
◽
On Chip
Download Full-text
Estimation of Optimized Energy and Latency Constraint for Task Allocation in 3d Network on Chip
International Journal of Computer Science and Information Technology
◽
10.5121/ijcsit.2014.6205
◽
2014
◽
Vol 6
(2)
◽
pp. 67-86
Author(s):
Vaibhav Jha
◽
Mohit Jha
◽
G K Sharma
Keyword(s):
Task Allocation
◽
Network On Chip
◽
3D Network
◽
On Chip
Download Full-text
A case of area- and energy-efficient heterogeneous mesh network-on-chip
Proceedings of the 3rd International Conference on Computer Science and Service System
◽
10.2991/csss-14.2014.38
◽
2014
◽
Author(s):
Jili Yan
◽
Guoming Lai
◽
Xiaola Lin
Keyword(s):
Energy Efficient
◽
Network On Chip
◽
Mesh Network
◽
On Chip
Download Full-text
Application-specific 3D Network-on-Chip design using simulated allocation
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
◽
10.1109/aspdac.2010.5419830
◽
2010
◽
Cited By ~ 4
Author(s):
Pingqiang Zhou
◽
Ping-Hung Yuh
◽
Sachin S. Sapatnekar
Keyword(s):
Network On Chip
◽
Chip Design
◽
3D Network
◽
On Chip
◽
Application Specific
Download Full-text
A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias
Proceedings of the 3rd International Workshop on Many-core Embedded Systems - MES '15
◽
10.1145/2768177.2768178
◽
2015
◽
Cited By ~ 1
Author(s):
Mostafa Said
◽
Farhad Mehdipour
◽
Kazuaki Murakami
◽
Mohamed El-Sayed
Keyword(s):
Design Methodology
◽
Network On Chip
◽
Through Silicon Vias
◽
3D Network
◽
On Chip
◽
Silicon Vias
Download Full-text
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