Improving Flash Translation Layer Performance by Using Log Block Mapping Scheme and Two-level Buffer for Address Translation Information

2019 ◽  
Author(s):  
Yinxia Xu
Keyword(s):  
Address Translation ◽  
Flash Translation Layer ◽  
Mapping Scheme

A Simplified Model of Write Amplification for Solid State Drives Adopting Page-Level Address Translation Mechanism

2011 ◽  
Vol 383-390 ◽  
pp. 2156-2160
Author(s):  
Wei Neng Wang ◽  
Zong Chao Wang ◽  
Kai Ni ◽  
Yi Zhao ◽  
Jian She Ma ◽  
...  
Keyword(s):  
Solid State ◽  
Probability Model ◽  
Storage Device ◽  
Solid State Drives ◽  
Address Translation ◽  
Write Amplification ◽  
Translation Mechanism ◽  
Shock Resistance ◽  
Parameter Ranges ◽  
Mapping Scheme

Due to its advantages, such as shock resistance, low power consumption, and so on, solid state drives are considered as a next generation storage device. And write amplification is a very import system parameter for evaluating performance. To simplify the analytical model of write amplification for solid state drives adopting page-level address translation mechanism, this paper proposes a probability model. Furthermore, numerical results based on our proposed probability model are also obtained. This paper can pose as a guideline for a first-order estimation of the write amplification for parameter ranges in solid state drives taking page mapping scheme.

GFTL: Group-Level Mapping in Flash Translation Layer to Provide Efficient Address Translation for NAND Flash-Based SSDs

2020 ◽  
Vol 66 (3) ◽  
pp. 242-250 ◽  
Author(s):  
Yubiao Pan ◽  
Yongkun Li ◽  
Huizhen Zhang ◽  
Hao Chen ◽  
Mingwei Lin
Keyword(s):  
Nand Flash ◽  
Group Level ◽  
Address Translation ◽  
Flash Translation Layer

Analysis of Oversampling Effect on Selected Mapping Scheme Using CORR Metric

2016 ◽  
Vol E99.B (2) ◽  
pp. 364-369
Author(s):  
Jun-Young WOO ◽  
Kee-Hoon KIM ◽  
Kang-Seok LEE ◽  
Jong-Seon NO ◽  
Dong-Joon SHIN
Keyword(s):  
Mapping Scheme

Architectural support for address translation on GPUs

2014 ◽  
Vol 49 (4) ◽  
pp. 743-758 ◽  
Author(s):  
Bharath Pichai ◽  
Lisa Hsu ◽  
Abhishek Bhattacharjee
Keyword(s):  
Architectural Support ◽  
Address Translation

Architectural support for address translation on GPUs

2014 ◽  
Vol 42 (1) ◽  
pp. 743-758 ◽  
Author(s):  
Bharath Pichai ◽  
Lisa Hsu ◽  
Abhishek Bhattacharjee
Keyword(s):  
Architectural Support ◽  
Address Translation
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