An out-of-order execution technique for runtime binary translators

1998 ◽  
Vol 32 (5) ◽  
pp. 151-158 ◽  
Author(s):  
Bich C. Le
2020 ◽  
pp. 1-8
Author(s):  
Raluca Tanasa

Throws and catches in rhythmic gymnastics represent one of the fundamental groups of apparatus actuation. They represent for the hoop actions of great showmanship, but also elements of risk. The purpose of this paper is to improve the throw execution technique through biomechanical analysis in order to increase the performance of female gymnasts in competitions. The subjects of this study were 8 gymnasts aged 9-10 years old, practiced performance Rhythmic Gymnastics. The experiment consisted in video recording and the biomechanical analysis of the element “Hoop throw, step jump and catch”. After processing the video recordings using the Simi Motion software, we have calculated and obtained values concerning: launch height, horizontal distance and throwing angle between the arm and the horizontal. Pursuant to the data obtained, we have designed a series of means to improve the execution technique for the elements comprised within the research and we have implemented them in the training process. Regarding the interpretation of the results, it may be highlighted as follows: height and horizontal distance in this element have values of the correlation coefficient of 0.438 and 0.323, thus a mean significance of 0.005. The values of the arm/horizontal angle have improved for all the gymnasts, the correlation coefficient being 0.931, with a significance of 0.01. As a general conclusion, after the results obtained, it may be stated that the means introduced in the experiment have proven their efficacy, which has led to the optimisation of the execution technique, thus confirming the research hypothesis.


1993 ◽  
Vol 42 (1) ◽  
pp. 122-127 ◽  
Author(s):  
H.C. Torng ◽  
M. Day

1992 ◽  
Vol 14 (2) ◽  
pp. 281 ◽  
Author(s):  
Thomas V. Greer ◽  
B. Wade Brorsen ◽  
Shi-Miin Liu
Keyword(s):  

2012 ◽  
Vol 2012 ◽  
pp. 1-12 ◽  
Author(s):  
Kaveh Aasaraai ◽  
Andreas Moshovos

Soft processors often use data caches to reduce the gap between processor and main memory speeds. To achieve high efficiency, simple, blocking caches are used. Such caches are not appropriate for processor designs such as Runahead and out-of-order execution that require nonblocking caches to tolerate main memory latencies. Instead, these processors use non-blocking caches to extract memory level parallelism and improve performance. However, conventional non-blocking cache designs are expensive and slow on FPGAs as they use content-addressable memories (CAMs). This work proposes NCOR, an FPGA-friendly non-blocking cache that exploits the key properties of Runahead execution. NCOR does not require CAMs and utilizes smart cache controllers. A 4 KB NCOR operates at 329 MHz on Stratix III FPGAs while it uses only 270 logic elements. A 32 KB NCOR operates at 278 Mhz and uses 269 logic elements.


Author(s):  
Arvind Singh Rawat ◽  
Arti Rana ◽  
Adesh Kumar ◽  
Ashish Bagwari

Basic hardware comprehension of an artificial neural network (ANN), to a major scale depends on the proficientrealization of a distinctneuron. For hardware execution of NNs, mostly FPGA-designed reconfigurable computing systems are favorable .FPGA comprehension of ANNs through a hugeamount of neurons is mainlyan exigentassignment. This workconverses the reviews on various research articles of neural networks whose concernsfocused in execution of more than one input neuron and multilayer with or without linearity property by using FPGA. An execution technique through reserve substitution isprojected to adjust signed decimal facts. A detailed review of many research papers have been done for the <br /> proposed work.


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