In-Situ HCl Etching and Selective Epitaxial Growth of B-doped Ge for the Formation of Recessed and Raised Sources and Drains

In this paper, the issues related to in-situ doping of silicon carbide (SiC) semiconductor during epitaxial growth are reviewed. Some of these issues can find solution by using an original approach called vapour-liquid-solid (VLS) mechanism. In this technique, the SiC seed is covered by a Sibased melt and is fed by propane in order to growth the epitaxial film. Using Al-Si melts and temperatures as low as 1100°C, very high p type doping was demonstrated, with a record value of 1.1021 at.cm-3. It leads to very low contact resistivity and even to metallic behaviour of the SiC deposit even at low temperature. Using Ge-Si melts, non intentionally low doped n type layers are grown. By forming Si-containing liquid droplets on a SiC seed, one can extrapolate this VLS growth to selective epitaxial growth (SEG). Such approach was successfully applied for both Al and Ge-based systems in order to form p+ and n doped areas respectively.

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Atmospheric In-situ Arsenic-Doped SiGe Selective Epitaxial Growth for Raised Extension NMOSFET

10.7567/ssdm.2006.e-5-1 ◽

2006 ◽

Author(s):

Tetsuya Ikuta ◽

Yuki Miyanami ◽

Shigeru Fujita ◽

Hayato Iwamoto ◽

Shingo Kadomura

Keyword(s):

Epitaxial Growth ◽

Selective Epitaxial Growth

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Recessed and Epitaxially Regrown SiGe(B) Source/Drain Junctions with Ni salicide contacts

MRS Proceedings ◽

10.1557/proc-810-c2.3 ◽

2004 ◽

Vol 810 ◽

Author(s):

Christian Isheden ◽

Per-Erik Hellström ◽

Henry H. Radamson ◽

Mikael Östling

Keyword(s):

Epitaxial Growth ◽

Silicon Substrate ◽

Solid Solubility ◽

Process Flow ◽

Dopant Activation ◽

Selective Epitaxial Growth ◽

Ion Implanted

ABSTRACTIntegration issues concerning recessed epitaxial SiGe(B) source/drain junctions formed by selective Si etching followed by selective epitaxial growth of in situ heavily B-doped Si1−xGex are presented. The concept is beneficial compared to conventional ion implanted junctions, since dopant activation above the solid solubility in Si can be obtained. When integrated in the PMOS process flow, the resulting Si1−xGex layer is very rough. Several possible causes for low quality epitaxy are discussed and improvements are proposed. It is suggested that the dopant type and/or concentration in the silicon substrate can have an effect on the process.

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Selective Epitaxial Growth Followed by in Situ Deposition of a- or Poly-Si for Seeded Soi.

MRS Proceedings ◽

10.1557/proc-107-231 ◽

1987 ◽

Vol 107 ◽

Cited By ~ 1

Author(s):

L. Karapiperis ◽

G. Garry ◽

D. Dieumegard

Keyword(s):

Epitaxial Growth ◽

Solid Phase ◽

Zone Melting ◽

Solid Phase Epitaxy ◽

3D Integration ◽

Thermal Budget ◽

Selective Epitaxial Growth ◽

In Situ Deposition ◽

Thermal Compatibility

AbstractSelective Epitaxial Growth (SEG) techniques find a growing number of applications in the field of Si IC's, such as, lateral isolation, vertical interconnects, seeded recrystallisation etc. In the present work, the use of Si SEG by CVD combined with in-situ deposition of a- or poly-Si for the improvement of SOI obtained by Zone Melting Recrystallisation (ZMR) or by Lateral Solid Phase Epitaxy (SPE) is described. The principle application for which the present work is intended is Three Dimentional (3D) Integration. One of the main constraints imposed on process is thermal compatibility with previously executed process steps. Hence the need to reduce the thermal budget for the Selective Epitaxial Growth as much as possible.

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