scholarly journals RT Component Sets for High-Level Design Applications

VLSI Design ◽  
1997 ◽  
Vol 5 (2) ◽  
pp. 155-165 ◽  
Author(s):  
Nikil D. Dutt ◽  
Pradip K. Jha

The system-level design process typically involves refining a design specification down to the point where each of the system's components is described as a block diagram or netlist of abstract Register-Transfer (RT) level components. In this paper, we motivate the need for such a standard RT component set, and describe a library environment that supports automatic model generation, design reuse, and synthesis with technology-specific estimators. We demonstrate the efficacy of the standard RT-component set approach with experiments performed on the HLSW92 benchmarks. Our preliminary results indicate only a small overhead of about 10% in using these standard, generic components. We then describe an automatic model generation and technology projection scheme that uses fast (on-line) estimators for predicting the area and delay of generic RT components tuned to a particular technology library with an accuracy of 10%. These model generators and estimators have been integrated with a high-level synthesis system at U.C. Irvine.

2012 ◽  
Vol 21 (07) ◽  
pp. 1250058
Author(s):  
BINGBING XIA ◽  
FEI QIAO ◽  
ZIDONG DU ◽  
DI ZHU ◽  
HUAZHONG YANG

H.264 video decoder is a good choice for embedded video processing applications because of its higher compression ratio than MPEG2, although it has higher requirements of run-time computational resource. Multi-core system is the future of the embedded processor design for its power efficiency and multi-thread parallelization capability, and can be used to fit well with the requirements for such video processing algorithms. To simulate and evaluate the performance of these multi-core systems effectively, a design flow at the system level is developed, at the higher level, the combination of TLM language (SystemC) and shared-memory parallel programming model (OpenMP) is used for such transaction-level simulation, and at the lower level, a multi-core simulator based on the extension of the SimpleScalar 3.0 ToolSet is developed for the cycle-accurate level simulation. Compared with other high-level simulation methods, ours has the ability to realize the true-parallelization simulation. What is more, experiments show that such simulation methodology can effectively simulate these complex multi-core applications in a short time to get the appropriate core number and the task allocation strategy (much less than RTL-level simulation) and the results can get at less than 15% deviated from the ideal ones calculated based on Amadal's Law, so the parallelization strategy obtained from such simulation is the best one that can be further applied for the RTL-level design of the final multi-core system.


2007 ◽  
Vol 33 (4) ◽  
pp. 249-268 ◽  
Author(s):  
N. Gorse ◽  
P. Bélanger ◽  
A. Chureau ◽  
E.M. Aboulhamid ◽  
Y. Savaria

2008 ◽  
Vol 17 (04) ◽  
pp. 703-727 ◽  
Author(s):  
JOZE DEDIC ◽  
MATJAZ FINC ◽  
ANDREJ TROST

The complexity of modern embedded systems requires a revised and systematic approach to efficient and concurrent management of hardware (HW) and software (SW) parts in a codesign process. In order to optimally meet the ever-increasing design requirements and at the same time leverage design productivity, higher level aspects need to be addressed before worrying about the HW/SW boundary. This paper deals with high-level aspects of system-level modeling and provides modeling extension, from which contemporary related methodologies can greatly benefit. High-level aspects, their influence on the entire design flow, and systematic integration into the codesign environment are presented. An approach is proposed with a higher level of abstraction that helps bridge the gap between informal and formal system specifications. Higher level design decisions are enabled, avoiding premature ad hoc design decisions. Applicability of the proposed high-level codesign concepts is illustrated with a case study.


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