scholarly journals Simulation of Open Circuit Voltage Decay for Solar Cell Determination of the Base Minority Carrier Lifetime and the Back Surface Recombination Velocity

1997 ◽  
Vol 19 (4) ◽  
pp. 225-238
Author(s):  
B. Affour ◽  
P. Mialhe
Keyword(s):  
Open Circuit Voltage ◽  
Minority Carrier ◽  
Surface Recombination ◽  
Minority Carrier Lifetime ◽  
Open Circuit ◽  
Surface Recombination Velocity ◽  
Back Surface ◽  
Voltage Decay ◽  
Recombination Velocity

The Open Circuit Voltage Decay (OCVD) method for the determination of the base minority carrier lifetime (τ) and the back surface recombination velocity (S) of silicon solar cells has been investigated at constant illumination level. The validity of the method has been discussed through a simulation study by considering the mathematical solution of the continuity equation. Extracted values ofτand S are compared to their input values in order to evaluate the performances of our method and the precision with regard to cell structural parameters, namely the base width and the base doping level. Deviations in lifetime values remain lower than 7% for almost all the cell configurations while recombination velocity deviations are shown to be dependent on cell structure parameters and experimental procedure.

High Open-Circuit Voltage in Silicon Heterojunction Solar Cells

2007 ◽  
Vol 989 ◽  
Author(s):  
Qi Wang ◽  
Matt R. Page ◽  
Eugene Iwancizko ◽  
Yueqin Xu ◽  
Lorenzo Roybal ◽  
...  
Keyword(s):  
Amorphous Silicon ◽  
Open Circuit Voltage ◽  
Surface Recombination ◽  
Open Circuit ◽  
Surface Recombination Velocity ◽  
Back Surface ◽  
Float Zone ◽  
Double Heterojunction ◽  
Type C ◽  
Recombination Velocity

AbstractHigh open-circuit voltage (Voc) silicon heterojunction (SHJ) solar cells are fabricated in double-heterojunction a-Si:H/c-Si/a-Si:H structures using low temperature (<225°C) hydrogenated amorphous silicon (a-Si:H) contacts deposited by hot-wire chemical vapor deposition (HWCVD). On p-type c-Si float-zone wafers, we used an amorphous n/i contact to the top surface and an i/p contact to the back surface to obtain a Voc of 667 mV in a 1 cm2 cell with an efficiency of 18.2%. This is the best reported p-type SHJ voltage. In our labs, it improves over the 652 mV cell obtained with a front amorphous n/i heterojunction emitter and a high-temperature alloyed Al back-surface-field contact. On n-type c-Si float-zone wafers, we used an a Si:H (p/i) front emitter and an a-Si:H (i/n) back contact to achieve a Voc of 691 mV on 1 cm2 cell. Though not as high as the 730 mV reported by Sanyo on n-wafers, this is the highest reported Voc for SHJ c-Si cells processed by the HWCVD technique. We found that effective c-Si surface cleaning and a double-heterojunction are keys to obtaining high Voc. Transmission electron microscopy reveals that high Voc cells require an abrupt interface from c-Si to a-Si:H. If the transition from the base wafer to the a-Si:H incorporates either microcrystalline or epitaxial Si at c Si interface, a low Voc will result. Lifetime measurement shows that the back-surface-recombination velocity (BSRV) can be reduced to ~15 cm/s through a-Si:H passivation. Amorphous silicon heterojunction layers on crystalline wafers thus combine low-surface recombination velocity with excellent carrier extraction.

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