Supporting Symmetric 128-bit AES in Networked Embedded Systems: An Elliptic Curve Key Establishment Protocol-on-Chip

2007 ◽  
Vol 2007 ◽  
pp. 1-9 ◽  
Author(s):  
Roshan Duraisamy ◽  
Zoran Salcic ◽  
Maurizio Adriano Strangio ◽  
Miguel Morales-Sandoval
Keyword(s):  
Embedded Systems ◽  
Elliptic Curve ◽  
Key Establishment ◽  
Networked Embedded Systems ◽  
On Chip

Supporting Symmetric 128-bit AES in Networked Embedded Systems: An Elliptic Curve Key Establishment Protocol-on-Chip

2007 ◽  
Vol 2007 (1) ◽  
pp. 065751 ◽  
Author(s):  
Roshan Duraisamy ◽  
Zoran Salcic ◽  
MaurizioAdriano Strangio ◽  
Miguel Morales-Sandoval
Keyword(s):  
Embedded Systems ◽  
Elliptic Curve ◽  
Key Establishment ◽  
Networked Embedded Systems ◽  
On Chip

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

A Prim-Dijkstra Algorithm for Multi-Hop Calibration of Networked Embedded Systems

2021 ◽  
pp. 1-1
Author(s):  
Valerio Freschi ◽  
Emanuele Lattanzi
Keyword(s):  
Embedded Systems ◽  
Dijkstra Algorithm ◽  
Networked Embedded Systems

High-Speed On-Chip Event Counters for Embedded Systems

2009 ◽  
Author(s):  
Nilanjan Mukherjee ◽  
Artur Pogiel ◽  
Janusz Rajski ◽  
Jerzy Tyszer
Keyword(s):  
Embedded Systems ◽  
High Speed ◽  
On Chip

scholarly journals Communication-Driven Automatic Virtual Prototyping for Networked Embedded Systems

2014 ◽  
Author(s):  
Liyuan Zhang ◽  
Joachim Falk ◽  
Tobias Schwarzer ◽  
Michael Glass ◽  
Jurgen Teich
Keyword(s):  
Embedded Systems ◽  
Virtual Prototyping ◽  
Networked Embedded Systems
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