Improved Design of Bit Synchronization Clock Extraction in Digital Communication System

An improved method is proposed in this design to reduce the phase jitter after the synchronization or the random noise induced phase jitter in a bit synchronization clock extraction circuit. By using a newly added digital filter between the phase detector and the controller, the phase difference pulses from the phase detector are counted and processed, before being transmitted to the controller for adjusting the phase of the output clock. The design is completed by using FPGA chip and VHDL hardware description language and performs the simulation verification on Quartus II. The results show that the improved system performs the accurate extraction of bit synchronized clock, reduces the phase jitter problem, improves the system running efficiency and the ability of anti-interference, and guarantees the synchronization performance of the digital communication system.