Research and Design of Digital Clock Based on FPGA

2011 ◽  
Vol 187 ◽  
pp. 741-745 ◽  
Author(s):  
Juan Hua Zhu ◽  
Ang Wu ◽  
Juan Fang Zhu
Keyword(s):  
Design Method ◽  
Display Time ◽  
Development Environment ◽  
Display Module ◽  
Digital Clock ◽  
Clock System ◽  
Quartus Ii ◽  
Hardware Description ◽  
Fpga Chip ◽  
Led Lights

A digital clock system designed by using VHDL hardware description language is presented in this paper. The proposed architecture fully utilizes the digital clock system available on FPGA chips based top-down design method in the Quartus II development environment. The Clock system is divided into four design modules: core module, frequency_division module, display module and tune module. It not only can time accurately and display time, but also can reset and adjust time. The LED lights will flash and the loudspeaker will tell time on the hour. The architecture is implemented and verified experimentally on a FPGA board. Because of the universality of digital clock and the portability of VHDL language, it can be applied directly in various designs based on FPGA chip.

Design and Implementation of the Infrared Remote-Controlled Digital Clock Based on FPGA

2015 ◽  
Vol 738-739 ◽  
pp. 1266-1269
Author(s):  
Jun Yang ◽  
Hong Ye Li ◽  
Long Liu
Keyword(s):  
Simple Structure ◽  
Digital Circuit ◽  
Description Language ◽  
Digital Clock ◽  
Development Cycle ◽  
Short Development Cycle ◽  
Quartus Ii ◽  
Function Modules ◽  
Hardware Description ◽  
And Function

The digital clock is a clock designed by digital circuit. Now, there are some limitations in the use and regulation of the digital clock in the large square. In this paper, the infrared remote-controlled digital clock based on FPGA can solve this problem well. This digital clock is composed of three parts: infrared remote control module, main circuit of the digital clock and function modules. And it is designed by the VHDL hardware description language, in the Quartus II software development environment.In addition, the digital clock has many extended functions, such as the hour timekeeping, alarm clock and temperature measuring. Besides, it has many advantages, including stable system , simple structure, short development cycle, fast speed and the strong usability.

Study on Mechanical and Electrical Automation with System Design of Frequency Meter Based on EDA Technology

2013 ◽  
Vol 387 ◽  
pp. 356-359
Author(s):  
Lin Jin ◽  
Qiang Liu
Keyword(s):  
Design System ◽  
Measuring Instruments ◽  
Description Language ◽  
Electronic Measuring ◽  
Display Module ◽  
Quartus Ii ◽  
Frequency Module ◽  
Hardware Description ◽  
Frequency Meter ◽  
Hardware Circuit

Frequency meter as a kind of electronic measuring instruments, have been widely applied in the field of Mechanical and Electrical automation. The design of a frequency meter based on EDA technology, is implemented in EDA software platform of Quartus II, using hardware description language (HDL) editor can also be seasonal schematic, design, system hardware circuit compiler, simulation, system is divided into five modules: frequency module, control module, counting module, range switching module and display module, the hardware design requires a download chip EPM7128S and input and output circuit.

scholarly journals Improved Design of Bit Synchronization Clock Extraction in Digital Communication System

2018 ◽  
Vol 2018 ◽  
pp. 1-8
Author(s):  
Huimin Duan ◽  
Hui Huang ◽  
Cuihua Li
Keyword(s):  
Communication System ◽  
Digital Communication ◽  
Random Noise ◽  
Phase Detector ◽  
Phase Jitter ◽  
Quartus Ii ◽  
Hardware Description ◽  
Fpga Chip ◽  
Digital Communication System ◽  
Improved Design

An improved method is proposed in this design to reduce the phase jitter after the synchronization or the random noise induced phase jitter in a bit synchronization clock extraction circuit. By using a newly added digital filter between the phase detector and the controller, the phase difference pulses from the phase detector are counted and processed, before being transmitted to the controller for adjusting the phase of the output clock. The design is completed by using FPGA chip and VHDL hardware description language and performs the simulation verification on Quartus II. The results show that the improved system performs the accurate extraction of bit synchronized clock, reduces the phase jitter problem, improves the system running efficiency and the ability of anti-interference, and guarantees the synchronization performance of the digital communication system.

Development of Configuration Software Interface for Engineering Vehicle Supervisory Control and Management

2011 ◽  
Vol 128-129 ◽  
pp. 1143-1146
Author(s):  
Hai Bin Yuan ◽  
Hui Feng Xiang
Keyword(s):  
Control Function ◽  
Design Method ◽  
Configuration Software ◽  
Object Oriented Programming ◽  
Design And Development ◽  
Development Environment ◽  
Software Interface ◽  
Heavy Duty Vehicle ◽  
Display Performance ◽  
Control And Management

The design and development of embedded configuration software is becoming one of the most important issues, the aim is to achieve mission-specific tasks and integrate supervisory management and control function in a collaborative way. In order to deal with the design and development of configure software for heavy-duty vehicle, object-oriented programming method is employed. At the same time, graphic-based display is realized using class object conception, and double buffering mechanism is proposed to improve graph display performance, furthermore, XML based serialization is employed to store the graph repository. The development environment and entire design process are based on the c sharp platform to take advantages of compatibility and scalability as well as meet further improvement. A snapshot of the graphic interface realization is shown to validate the design method.

Research and Design of Asynchronous FIFO Based on FPGA

2014 ◽  
Vol 644-650 ◽  
pp. 3440-3444
Author(s):  
Bing Qi Liu ◽  
Ming Zhe Liu ◽  
Gang Yang ◽  
Xiao Bo Mao ◽  
Huai Liang Li
Keyword(s):  
Design Method ◽  
Stable State ◽  
Gray Code ◽  
Validity And Reliability ◽  
Verilog Hdl ◽  
Simulation Test ◽  
Development Platform ◽  
Module Design ◽  
Quartus Ii ◽  
Research And Design

In this article, a design method of asynchronous FIFO memory based on FPGA is put forward. With FPGA as the core controller, We adopt Verilog HDL and top-down design method to build a top-level module design and also analyze the mark logic of asynchronous FIFO and the elimination of semi-stable state under Quartus II development platform. Besides, with the application of Gray code conversion technology, not only the reliable transmission of data is guaranteed but also design efficiency is improved. Through contrast experiment analysis and simulation test, the validity and reliability of asynchronous FIFO memory are verified, meeting the basic requirement that FIFO can hold more enough data without spillovers despite the fullness of data.

scholarly journals Modelling Gene-Protein-Reaction Associations on an FPGA

2019 ◽  
Author(s):  
Macauley Coggins
Keyword(s):  
Metabolic Model ◽  
Logic Device ◽  
Description Language ◽  
Metabolic Modelling ◽  
Quartus Ii ◽  
Hardware Description ◽  
Design Software ◽  
Genome Scale ◽  
The Relationship ◽  
Protein Reaction

Genome-Scale metabolic models have proven to be incredibly useful.Allowing researchers to model cellular functionality based upon gene expression. However as the number of genes and reactions increases it can become computationally demanding. The first step in genome-scale metabolic modelling is to model the relationship between genes and reactions in the form of Gene-Protein-Reaction Associations (GPRA). In this research we have developed a way to model GPRAs on an Altera Cyclone II FPGA using Quartus II programmable logic device design software and the VHDL hardware description language. The model consisting of 7 genes and 7 reactions was implemented using 7 combinational functions and 14 I/O pins. This model will be the first step towards creating a full genome scale metabolic model on FPGA devices which we will be fully investigating in future studies.

scholarly journals DARTSVIEW, A TOOLKIT FOR DARTS IN LABVIEW

2009 ◽  
Vol 12 (14) ◽  
pp. 69-76
Author(s):  
Hieu Khanh Ngo ◽  
Grolleau Emmanuel
Keyword(s):  
Real Time ◽  
Virtual Instrument ◽  
Design Method ◽  
Real Time Systems ◽  
Application Development ◽  
Development Environment ◽  
Real Time System ◽  
Temporal Validation ◽  
Control Command ◽  
Time Systems

DARTS (Design Approach for Real Time Systems) [4] is a software design method for real time systems. LabVIEW (Laboratory Virtual Instrument Engineering Workbench) is a graphical application development environment developed by National Instruments Corporation based on the dataflow representation of the "G" language [6][2]. LabVIEW is implicitly multithreaded and has high level functions for communication/synchronization, allowing it to be used as a programming language for control/command and soft real-time applications. In order to help a designer to develop a real-time application, we propose the library DARTSVIEW, which simplifies the passage from the conception of a "multitasking" application to the implementation [8). One can use DARTSVIEW in different phases of the life cycle of real-time system software. The last version of DARTSVIEW, allows to define in XML several real-time programming normalized languages, and to generate a part of the code for different specific programming languages (Ada, POSIX 1003.1, VxWorks, OSEK/VDX, etc.). The flexibility introduced by the use of XML allows a designer also to generate some code targeting real-time scheduling analysis tools in order to achieve the temporal validation. The objective of this article is to present an overview of DARTSVIEW, a Toolkit for DARTS in LabVIEW, the role of DARTSVIEW in the software.

Research and Design of Beamforming Device of SLC-LSCMA Algorithm Based on FPGA

2013 ◽  
Vol 347-350 ◽  
pp. 1677-1681
Author(s):  
Qing Fang Zhou ◽  
Yan Yan Yu ◽  
Lei Wang ◽  
Jun Yang
Keyword(s):  
Least Squares ◽  
Satellite Communications ◽  
Clock Frequency ◽  
Verilog Hdl ◽  
Description Language ◽  
Quartus Ii ◽  
Hardware Description ◽  
Timing Simulation ◽  
Array Beamforming ◽  
Research And Design

In this paper,we design a uniform circular array beamforming device of 16 yuan based on the least squares SLC-LSCMA algorithm (based on the linear subspace constrained least squares cma) high stability and rapid convergence for the foundation. The design of the complete beam-forming the SLC-LSCMA algorithm by plural, time-multiplier and accumulators, which uses less resources and faster than the traditional algorithm. The beamforming device uses hardware description language of Verilog HDL , and wires on the QUARTUS II 8.0. Finally the beamforming device is downloaded to the Alteras EP2C35F672C6, and its timing simulation can be run properly in the 50MHz clock frequency. This design can be widely used in mobile communication and satellite communications.

Second Development of Panel Furniture Based on Pro/E

2013 ◽  
Vol 712-715 ◽  
pp. 1189-1193
Author(s):  
Yan Hong Yang ◽  
Xiang Qiang Zhong
Keyword(s):  
Program Verification ◽  
Modular Design ◽  
Parametric Design ◽  
Design Method ◽  
Design System ◽  
Development Mode ◽  
Dynamic Link Library ◽  
Development Environment ◽  
Second Development ◽  
Synchronous Development

The parametric design and second development flow of panel furniture are analyzed based on Pro/E and modular design method. It created manage database of panel furniture based on SQL2000 and ADO technology, it analyzed synchronous development mode of Pro/TOOLKIT, menu design and DLL dynamic link library development were talked, the parametric design system of hall cabinet, bedside cabinet and wardrobe under VC ++6.0 development environment was developed. Throng example program verification, the method is feasible; it can rapidly finish panel furniture models, and improve the designer's working efficiency.

FPGA-BASED MOTION CONTROLLER FOR WAFER-HANDLING ROBOT

2013 ◽  
Vol 37 (3) ◽  
pp. 427-437
Author(s):  
Hsin-Hung Chou ◽  
Ying-Shieh Kung ◽  
Tai-Wei Tsui ◽  
Stone Cheng
Keyword(s):  
Hardware Description Language ◽  
Motion Controller ◽  
Description Language ◽  
Gate Arrays ◽  
Current Vector ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Axis Position ◽  
Hardware Description ◽  
Fpga Chip

This study applies FPGA (Field Programmable Gate Arrays) technology to implement a motion controller for wafer-handling robot which has three-DOF (Degree of Freedom) motion. The proposed FPGA-based motion controller has two modules. The first module is Nios II processor which is used to realize the motion trajectory computation and the three-axis position/speed controllers. The second module is demonstrated to implement the three-axis current vector controllers by using FPGA hardware, and VHDL (VHSIC Hardware Description Language) is adopted to describe the controller behavior. Therefore, a fully digital motion controller for wafer-handling robot, such as one trajectory planning, three current vector controllers and three position/speed controllers are all implemented with an FPGA chip.

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