scholarly journals Efficient Searchable Symmetric Encryption Supporting Dynamic Multikeyword Ranked Search

2020 ◽  
Vol 2020 ◽  
pp. 1-16
Author(s):  
Yu Zhang ◽  
Yin Li ◽  
Yifan Wang

Searchable symmetric encryption that supports dynamic multikeyword ranked search (SSE-DMKRS) has been intensively studied during recent years. Such a scheme allows data users to dynamically update documents and retrieve the most wanted documents efficiently. Previous schemes suffer from high computational costs since the time and space complexities of these schemes are linear with the size of the dictionary generated from the dataset. In this paper, by utilizing a shallow neural network model called “Word2vec” together with a balanced binary tree structure, we propose a highly efficient SSE-DMKRS scheme. The “Word2vec” tool can effectively convert the documents and queries into a group of vectors whose dimensions are much smaller than the size of the dictionary. As a result, we can significantly reduce the related space and time cost. Moreover, with the use of the tree-based index, our scheme can achieve a sublinear search time and support dynamic operations like insertion and deletion. Both theoretical and experimental analyses demonstrate that the efficiency of our scheme surpasses any other schemes of the same kind, so that it has a wide application prospect in the real world.

2012 ◽  
Vol 479-481 ◽  
pp. 1403-1408
Author(s):  
Gang Lian Zhao ◽  
Yi Jiang ◽  
Yu Jun Chen ◽  
Yan Li Ma

Based on software Pro/ENGINEER and Visual C++ 2005,sub-module of parametric design of assembly with wide universality was done by using Pro/TOOLKIT, and the design procedure was introduced in details. Assembly relation of sub-components is transformed into binary tree structure to store and search parts, and the assembly relation is displayed by CTreeCtrl control. The corresponding parts can be quickly found in the binary tree. Engineering drawing was automatically generated and displayed by ProductView after loading a part, and in this way dimensions of different parts can be modified according to engineering drawing in asynchronous mode. The sub-module can meet the needs of parametric design of parts in the integrated simulation system.


2020 ◽  
Vol 17 (6) ◽  
pp. 1322-1332 ◽  
Author(s):  
Xueqiao Liu ◽  
Guomin Yang ◽  
Yi Mu ◽  
Robert H. Deng

2015 ◽  
Vol 28 (2) ◽  
pp. 237-249 ◽  
Author(s):  
Rafał Długosz ◽  
Andrzej Rydlewski ◽  
Tomasz Talaśka

In this paper we propose novel, binary-tree, asynchronous, nonlinear filters suitable for signal processing realized at the transistor level. Two versions of the filter have been proposed, namely the dilatation (Max) and the erosion (Min) one. In the proposed circuits an input signal (current) is sampled in a delay line, controlled by a multiphase clock. In the subsequent stage particular samples are converted to 1-bit digital signals with delays proportional to the values of these samples. In the last step the delays are compared in digital binary-tree structure in order to find either the Min or the Max value, depending on which filter is used. Both circuits have been simulated in the TSMC CMOS 0.18?m technology. To make the results reliable we applied the corner analysis procedure. The circuits were tested for temperatures ranging from -40 to 120?C, for different transistor models and supply voltages. The circuits offer a precision of about 99% at a typical detection time of 20 ns (for the Max filter) and 100 ns for the Min filter (the worst case scenario). The energy consumed per one input during a single calculation cycle equals 0.32 and 1.57 pJ, for the Max and Min filters, respectively.


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