A Novel Approach for Reducing Energy Consumption using Binary Tree Structure in WSN

Author(s):  
Dharmendra Parmar ◽  
◽  
Jaimala Jha ◽  
2012 ◽  
Vol 479-481 ◽  
pp. 1403-1408
Author(s):  
Gang Lian Zhao ◽  
Yi Jiang ◽  
Yu Jun Chen ◽  
Yan Li Ma

Based on software Pro/ENGINEER and Visual C++ 2005,sub-module of parametric design of assembly with wide universality was done by using Pro/TOOLKIT, and the design procedure was introduced in details. Assembly relation of sub-components is transformed into binary tree structure to store and search parts, and the assembly relation is displayed by CTreeCtrl control. The corresponding parts can be quickly found in the binary tree. Engineering drawing was automatically generated and displayed by ProductView after loading a part, and in this way dimensions of different parts can be modified according to engineering drawing in asynchronous mode. The sub-module can meet the needs of parametric design of parts in the integrated simulation system.


1996 ◽  
Vol 29 (11) ◽  
pp. 1905-1917 ◽  
Author(s):  
Bing-Bing Chai ◽  
Tong Huang ◽  
Xinhua Zhuang ◽  
Yunxin Zhao ◽  
Jack Sklansky

Author(s):  
Jun Zhang ◽  
◽  
Jinglu Hu

In this paper, we propose a Hierarchical Frequency Sensitive Competitive Learning (HFSCL) method to achieve Color Quantization (CQ). In HFSCL, the appropriate number of quantized colors and the palette can be obtained by an adaptive procedure following a binary tree structure with nodes and layers. Starting from the root node that contains all colors in an image until all nodes are examined by split conditions, a binary tree will be generated. In each node of the tree, a Frequency Sensitive Competitive Learning (FSCL) network is used to achieve two-way division. To avoid over-split, merging condition is defined to merge the clusters that are close enough to each other at each layer. Experimental results show that the proposed HFSCL has desired ability for CQ.


2006 ◽  
Vol 17 (02) ◽  
pp. 271-285 ◽  
Author(s):  
KRISHNENDU ROY ◽  
RAMACHANDRAN VAIDYANATHAN ◽  
JERRY L. TRAHAN

Dynamically reconfigurable architectures offer extremely fast solutions to various problems. The Circuit Switched Tree (CST) is an important interconnect used to implement such architectures. A CST has a binary tree structure with processing elements (PEs) as leaves and switches as internal nodes. PEs communicate among themselves using the links of the tree. Key components for successful communication are scheduling individual communications and configuring the CST switches. This paper presents a scheduling and configuration algorithm for communications on a CST where conflicts necessitate multiple rounds of routing to perform all communications. The algorithm is distributed and requires only local information, yet it captures the global picture to ensure proper communication. The paper also explains how to apply the algorithm to an important class, "well-nested communications", for which the algorithm is optimal and efficient.


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