Fault simulation algorithm for transistor single stuck short faults

2021 ◽  
pp. 404-410
Author(s):  
Durgesh Addala ◽  
P. Teja ◽  
Sobhit Saxena
Keyword(s):  
Fault Simulation ◽  
Simulation Algorithm

Deductive fault simulation algorithm based on fault collapsing

1993 ◽  
Vol 8 (2) ◽  
pp. 182-187
Author(s):  
Gong Yunzhan ◽  
Wei Daozheng
Keyword(s):  
Fault Simulation ◽  
Simulation Algorithm

An efficient DC fault simulation algorithm for nonlinear circuits

1986 ◽  
Vol 3 (2) ◽  
pp. 90-97
Author(s):  
Lin Hua ◽  
Ling Xieting ◽  
Pan Mingde
Keyword(s):  
Fault Simulation ◽  
Nonlinear Circuits ◽  
Simulation Algorithm ◽  
Dc Fault

FAST FAULT SIMULATION ALGORITHM

10.12737/6684 ◽  
2014 ◽  
Vol 7 (3) ◽  
pp. 50-53
Author(s):  
Чевычелов ◽  
Yu. Chevychelov
Keyword(s):  
Digital Circuits ◽  
Fault Simulation ◽  
Temporal Analysis ◽  
Simulation Algorithm

We consider algorithms for logical-temporal analysis, fault simulation for the components of digital circuits. In this paper, the author offers an accelerated algorithm for fault simulation

The Fault Simulation Algorithm Based on Multiple Random Local Stresses Technique - The Tool for Detail Seismic Interpretation

2021 ◽  
Author(s):  
I.I. Priezzhev ◽  
D.A. Danko ◽  
U. Strecker ◽  
Y.Y. Taikulakov
Keyword(s):  
Fault Simulation ◽  
Seismic Interpretation ◽  
Simulation Algorithm ◽  
Local Stresses

scholarly journals Switch-level Differential Fault Simulation of MOS VLSI Circuits

VLSI Design ◽  
1996 ◽  
Vol 4 (3) ◽  
pp. 217-229
Author(s):  
Evstratios Vandris ◽  
Gerald Sobelman
Keyword(s):  
Fault Simulation ◽  
Simulation Method ◽  
Relative Strength ◽  
Vlsi Circuits ◽  
Simulation Algorithm ◽  
Dynamic Memory ◽  
Simulation Techniques ◽  
Circuit Component ◽  
Mos Circuits ◽  
Circuit Components

A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. Every compiled circuit component is assigned a dominance attribute, which abstracts relative strength information in the circuit. Dominance is used during simulation to resolve the X-state due to fighting pull-up and pull-down transistor paths and also to deduce transistor fault detectability and fault equivalencies prior to simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level. Differential fault simulation provides excellent performance with minimum memory requirements, although it incurs a higher overhead at the switch-level than at the gate-level due to the dynamic memory properties of MOS circuits.

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