Arduino-Based Fault Detection Schemes for DC Microgrids

This work considers industrial process monitoring using a variational autoencoder (VAE). As a powerful deep generative model, the variational autoencoder and its variants have become popular for process monitoring. However, its monitoring ability, especially its fault diagnosis ability, has not been well investigated. In this paper, the process modeling and monitoring capabilities of several VAE variants are comprehensively studied. First, fault detection schemes are defined in three distinct ways, considering latent, residual, and the combined domains. Afterwards, to conduct the fault diagnosis, we first define the deep contribution plot, and then a deep reconstruction-based contribution diagram is proposed for deep domains under the fault propagation mechanism. In a case study, the performance of the process monitoring capability of four deep VAE models, namely, the static VAE model, the dynamic VAE model, and the recurrent VAE models (LSTM-VAE and GRU-VAE), has been comparatively evaluated on the industrial benchmark Tennessee Eastman process. Results show that recurrent VAEs with a deep reconstruction-based diagnosis mechanism are recommended for industrial process monitoring tasks.

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A Probabilistic Approach for the Evaluation of Fault Detection Schemes in Microgrids

Engineering, Technology & Applied Science Research ◽

10.48084/etasr.1472 ◽

2017 ◽

Vol 7 (5) ◽

pp. 1967-1973 ◽

Cited By ~ 1

Author(s):

R. Eslami ◽

S. H. H. Sadeghi ◽

H. Askarian Abyaneh

Keyword(s):

Fault Detection ◽

Probabilistic Approach ◽

Successful Performance ◽

Three Phase ◽

Important Challenge ◽

Network Topologies ◽

Location Type ◽

High Degree ◽

Detection Schemes ◽

Very High

An important challenge in protection of a microgrid is the process of fault detection, considering the uncertainties in its topologies. Equally important is the evaluation of proposed methods as their incorrect performances could result in unreasonable power outages. In this paper, a new fault detection and characterization method is introduced and evaluated subject to the uncertainties of network topologies. The features of three-phase components together with the positive, negative and zero sequences of current and voltage waveforms are derived to detect the occurrence of a fault, its location, type and the engaged phases. The proposed method is independent of the microgrid topology. To evaluate the performance of the proposed method in various network topologies, a Monte Carlo scheme is developed. This is done by computing the expected energy not-supplied reliability index and the percentage of successful performance of the fault detection. Simulation results show that the proposed method can detect faults in various microgrid topologies with a very high degree of accuracy.

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A Hybrid Countermeasure-Based Fault-Resistant AES Implementation

Journal of Circuits System and Computers ◽

10.1142/s0218126620500449 ◽

2019 ◽

Vol 29 (03) ◽

pp. 2050044

Author(s):

Noura Benhadjyoussef ◽

Mouna Karmani ◽

Mohsen Machhout ◽

Belgacem Hamdi

Keyword(s):

Fault Detection ◽

Fault Analysis ◽

Advanced Encryption Standard ◽

Implementation Cost ◽

Additional Time ◽

Area Overhead ◽

Differential Fault Analysis ◽

Detection Capabilities ◽

Xilinx Fpga ◽

Detection Schemes

A Fault-Resistant scheme has been proposed to secure the Advanced Encryption Standard (AES) against Differential Fault Analysis (DFA) attack. In this paper, a hybrid countermeasure has been presented in order to protect a 32-bits AES architecture proposed for resource-constrained embedded systems. A comparative study between the most well-known fault detection schemes in terms of fault detection capabilities and implementation cost has been proposed. Based on this study, we propose a hybrid fault resistant scheme to secure the AES using the parity detection for linear operations and the time redundancy for SubBytes operation. The proposed scheme is implemented on the Virtex-5 Xilinx FPGA board in order to evaluate the efficiency of the proposed fault-resistant scheme in terms of area, time costs and fault coverage (FC). Experimental results prove that the countermeasure achieves a FC with about 98,82% of the injected faults detected during the 32-bits AES process. The area overhead of the proposed countermeasure is about 14% and the additional time delay is about 13%.

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Model-Based Fault Detection in DC Microgrids

2019 Smart Grid Conference (SGC) ◽

10.1109/sgc49328.2019.9056589 ◽

2019 ◽

Author(s):

Asaad Salimi ◽

Yazdan Batmani ◽

Hassan Bevrani

Keyword(s):

Fault Detection ◽

Dc Microgrids ◽

Model Based

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