Ultra-Low-Voltage Implementation of Neural Networks

Author(s):  
Farooq Ahmad Khanday ◽  
Nasir Ali Kant ◽  
Mohammad Rafiq Dar
Keyword(s):  
2021 ◽  
pp. 2100021
Author(s):  
Qingzhou Wan ◽  
Marco Rasetto ◽  
Mohammad T. Sharbati ◽  
John R. Erickson ◽  
Sridhar Reddy Velagala ◽  
...  

2019 ◽  
Vol 13 (2) ◽  
pp. 171-178
Author(s):  
Xiongwen Zhao ◽  
Hui Zhang ◽  
Liang Li ◽  
Wenbing Lu ◽  
Yi Ding ◽  
...  

2021 ◽  
Vol 28 (4) ◽  
pp. 21-30
Author(s):  
Mohy El-Din Abo El-sSoud ◽  
Hassan Soliman ◽  
Laila El-ghanam ◽  
Roshdy AbdelRassoul

2020 ◽  
Vol 3 (S1) ◽  
Author(s):  
Stephan Balduin ◽  
Tom Westermann ◽  
Erika Puiutta

Abstract The transition of the power grid requires new technologies and methodologies, which can only be developed and tested in simulations. Especially larger simulation setups with many levels of detail can become quite slow. Therefore, the number of possible simulation evaluations decreases. One solution to overcome this issue is to use surrogate models, i. e., data-driven approximations of (sub)systems. In a recent work, we built a surrogate model for a low voltage grid using artificial neural networks, which achieved satisfying results. However, there were still open questions regarding the assumptions and simplifications made. In this paper, we present the results of our ongoing research, which answer some of these questions. We compare different machine learning algorithms as surrogate models and exchange the grid topology and size. In a set of experiments, we show that algorithms based on linear regression and artificial neural networks yield the best results independent of the grid topology. Furthermore, adding volatile energy generation and a variable phase angle does not decrease the quality of the surrogate models.


2018 ◽  
Vol 2018 (15) ◽  
pp. 851-855 ◽  
Author(s):  
Marcello Mastroleo ◽  
Roberto Ugolotti ◽  
Luca Mussi ◽  
Emilio Vicari ◽  
Federico Sassi ◽  
...  

1998 ◽  
Vol 08 (05n06) ◽  
pp. 615-635 ◽  
Author(s):  
SAEID SADEGHI-EMAMCHAIE ◽  
G. A. JULLIEN ◽  
V. S. DIMITROV ◽  
W. C. MILLER

We discuss the realization of digital arithmetic using analog arrays in the form of Cellular Neural Networks (CNNs). These networks replace the fast switching nodes of logic gates with slewing nodes using current sources driving into capacitors; this provides both low current spikes and low voltage slewing rates, reducing system noise and cross-talk in low-voltage mixed-signal applications. In this paper we generalize the design methodology using a Symbolic Substitution (SS) technique, and we use a recently developed Double-Base Number System (DBNS) to illustrate our design technique. This choice is predicated on the fact that the DBNS representation is naturally 2-dimensional and excites more degrees of freedom in the design space. Spatial configurations of the recognition/replacement patterns used in SS are defined based on the properties of the DBNS arithmetic operation. The SS recognition phases are implemented by dynamic evaluation of simple conditions defined based on an analysis of the cell dynamic routes. The replacement phases are automatically executed through switching current which force the transition of cell state voltage between logic levels. In effect, we build self-timed logic arrays with all nodes in the system under controlled slew. Simulation results from schematic level designs are provided to demonstrate the effectiveness of the technique.


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