Real-time techniques and low-power architecture design for video coding

2016 ◽  
Author(s):  
Luheng Jia
Keyword(s):  
Low Power ◽  
Video Coding ◽  
Real Time ◽  
Architecture Design ◽  
Power Architecture

scholarly journals High Throughput and Low Cost Architecture for the Forward Quantization of the H.264/AVC Video Compression Standard

2010 ◽  
Vol 13 (3) ◽  
Author(s):  
Felipe Sampaio ◽  
Daniel Palomino ◽  
Robson Dornelles ◽  
Luciano Agostini
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Video Coding ◽  
Real Time ◽  
Video Compression ◽  
High Throughput ◽  
Low Cost ◽  
Standard Cell ◽  
Dedicated Hardware ◽  
Operation Frequency

This work presents a dedicated hardware design for the Forward Quantization Module (Q module) of the H.264/AVC Video Coding Standard, using optimized multipliers. The goal of this design is to achieve high throughput rates combined with low hardware consumption. The architecture was described in VHDL and synthesized to the EP2S60F1020C3 Altera Stratix II FPGA and to the TSMC 0.18μm Standard Cell technology. The architecture is able to operate at 364.2 MHz as a maximum operation frequency. At this frequency, the architecture is able to process 117 QHDTV frames (3840x2048 pixels) per second. The designed architecture can be used in low power and low cost applications, since it can process high resolution in real time even with very low operation frequencies and with low hardware consumption. In the comparison with related works, the designed Q module achieves the best results of throughput and hardware consumption.

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