Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96
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Published By IEEE Computer Soc. Press

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Finite word-length effects of an unified systolic array for 2-D DCT/IDCT

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96 ◽

10.1109/asap.1996.542799 ◽

2002 ◽

Cited By ~ 3

Author(s):

H. Lim ◽

C. Yim ◽

E.E. Swartzlander

Keyword(s):

Systolic Array ◽

Word Length ◽

Finite Word Length ◽

Finite Word ◽

Length Effects

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NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96 ◽

10.1109/asap.1996.542821 ◽

2002 ◽

Cited By ~ 156

Author(s):

K.M. Fant ◽

S.A. Brandt

Keyword(s):

Digital Circuit ◽

Circuit Synthesis ◽

Null Convention Logic

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Performance modeling and tradeoff analysis during rapid prototyping

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96 ◽

10.1109/asap.1996.542826 ◽

2002 ◽

Cited By ~ 2

Author(s):

J. Walrath ◽

S. Chatha ◽

R. Vemuri ◽

N. Narasimhan ◽

V. Srinivasan

Keyword(s):

Rapid Prototyping ◽

Performance Modeling ◽

Tradeoff Analysis

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Reconfigurable processing with field programmable gate arrays

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96 ◽

10.1109/asap.1996.542824 ◽

2002 ◽

Cited By ~ 4

Author(s):

B.K. Fawcett ◽

J. Watson

Keyword(s):

Field Programmable Gate Arrays ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Reconfigurable Processing

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A synthesis system for bus-based wavefront array architectures

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96 ◽

10.1109/asap.1996.542822 ◽

2002 ◽

Cited By ~ 1

Author(s):

R.W. Hartenstein ◽

J. Becker ◽

M. Herz ◽

R. Kress ◽

U. Nageldinger

Keyword(s):

Synthesis System

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Parametric analysis of polyhedral iteration spaces

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96 ◽

10.1109/asap.1996.542833 ◽

2002 ◽

Cited By ~ 8

Author(s):

P. Clauss ◽

V. Loechner

Keyword(s):

Parametric Analysis

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A VLSI system architecture for real-time intelligent decision making

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96 ◽

10.1109/asap.1996.542817 ◽

2002 ◽

Cited By ~ 2

Author(s):

M.I. Patel ◽

N. Ranganathan

Keyword(s):

Decision Making ◽

Real Time ◽

System Architecture ◽

Intelligent Decision Making ◽

Intelligent Decision ◽

Vlsi System

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A common architecture for the DWT and IDWT

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96 ◽

10.1109/asap.1996.542814 ◽

2002 ◽

Cited By ~ 8

Author(s):

M. Vishwanath ◽

R.M. Owens

Keyword(s):

Common Architecture

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Static communication scheduling for minimizing collisions in application specific parallel systems

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96 ◽

10.1109/asap.1996.542819 ◽

2002 ◽

Cited By ~ 1

Author(s):

D.R. Surma ◽

E.H.-M. Sha

Keyword(s):

Parallel Systems ◽

Communication Scheduling ◽

Application Specific

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A new Euclidean division algorithm for residue number systems

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96 ◽

10.1109/asap.1996.542800 ◽

2002 ◽

Cited By ~ 1

Author(s):

J.-C. Bajard ◽

L.-S. Didier ◽

J.-M. Muller

Keyword(s):

Division Algorithm ◽

Number Systems ◽

Residue Number Systems ◽

Residue Number

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Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Computer Soc. Press

Finite word-length effects of an unified systolic array for 2-D DCT/IDCT

NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis

Performance modeling and tradeoff analysis during rapid prototyping

Reconfigurable processing with field programmable gate arrays

A synthesis system for bus-based wavefront array architectures

Parametric analysis of polyhedral iteration spaces

A VLSI system architecture for real-time intelligent decision making

A common architecture for the DWT and IDWT

Static communication scheduling for minimizing collisions in application specific parallel systems

A new Euclidean division algorithm for residue number systems

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96
Latest Publications