A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache

IEICE Transactions on Electronics ◽

10.1587/transele.e92.c.517 ◽

2009 ◽

Vol E92-C (4) ◽

pp. 517-521

Author(s):

Gi-Ho PARK ◽

Jung-Wook PARK ◽

Hoi-Jin LEE ◽

Gunok JUNG ◽

Sung-Bae PARK ◽

...

Keyword(s):

Low Power ◽

Branch Prediction ◽

Instruction Cache

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Low-Power Design of Hybrid Instruction Cache Based on Branch Prediction and Drowsy Cache

The Proceedings of the Second International Conference on Communications, Signal Processing, and Systems - Lecture Notes in Electrical Engineering ◽

10.1007/978-3-319-00536-2_40 ◽

2013 ◽

pp. 335-343

Author(s):

Li Wei ◽

Xiao Jian-qing

Keyword(s):

Low Power ◽

Low Power Design ◽

Branch Prediction ◽

Hybrid Instruction ◽

Instruction Cache

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Branch prediction techniques for low-power VLIW processors

Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03 ◽

10.1145/764808.764866 ◽

2003 ◽

Author(s):

G. Palermo ◽

M. Sam ◽

C. Silvan ◽

V. Zaccari ◽

R. Zafalo

Keyword(s):

Low Power ◽

Branch Prediction ◽

Vliw Processors ◽

Prediction Techniques

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Low power branch prediction for embedded application processors

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design - ISLPED '10 ◽

10.1145/1840845.1840860 ◽

2010 ◽

Author(s):

Nadav Levison ◽

Shlomo Weiss

Keyword(s):

Low Power ◽

Branch Prediction ◽

Embedded Application

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Low-power, high-performance analog neural branch prediction

2008 41st IEEE/ACM International Symposium on Microarchitecture ◽

10.1109/micro.2008.4771812 ◽

2008 ◽

Author(s):

Renee St. Amant ◽

Daniel A. Jimenez ◽

Doug Burger

Keyword(s):

Low Power ◽

High Performance ◽

Branch Prediction

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A Low-Power Instruction Cache Design Based on Record Buffer

Journal of Computer Research and Development ◽

10.1360/crad20060426 ◽

2006 ◽

Vol 43 (4) ◽

pp. 744

Author(s):

Zhiqiang Ma

Keyword(s):

Low Power ◽

Instruction Cache ◽

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Branch Prediction-Directed Dynamic Instruction Cache Locking for Embedded Systems

ACM Transactions on Embedded Computing Systems ◽

10.1145/2660492 ◽

2014 ◽

Vol 13 (5s) ◽

pp. 1-24 ◽

Author(s):

Keni Qiu ◽

Mengying Zhao ◽

Chun Jason Xue ◽

Alex Orailoglu

Keyword(s):

Embedded Systems ◽

Branch Prediction ◽

Instruction Cache ◽

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A compiler-controlled instruction cache architecture for an embedded low power microprocessor

The Fifth International Conference on Computer and Information Technology (CIT'05) ◽

10.1109/cit.2005.3 ◽

2005 ◽

Author(s):

Xiaoping Zhu ◽

T.T. Tay

Keyword(s):

Low Power ◽

Instruction Cache ◽

Cache Architecture

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Low power instruction cache design based on branch execution tracks

2013 IEEE 10th International Conference on ASIC ◽

10.1109/asicon.2013.6811822 ◽

2013 ◽

Author(s):

Quanquan Li ◽

Qi Wang ◽

Tiejun Zhang ◽

Donghui Wang ◽

Chaohuan Hou

Keyword(s):

Low Power ◽

Instruction Cache ◽

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Low Power Instruction Cache with Word Selective Line Buffer

2012 IEEE 15th International Conference on Computational Science and Engineering ◽

10.1109/iccse.2012.37 ◽

2012 ◽

Author(s):

Hyun-Bum Cho ◽

Ju-Hee Choi ◽

Seong-Tea Jhang ◽

Chu-Shik Jhon

Keyword(s):

Low Power ◽

Instruction Cache

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Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints

Power-Aware Computer Systems - Lecture Notes in Computer Science ◽

10.1007/3-540-36612-1_2 ◽

2003 ◽

pp. 18-32

Author(s):

Koji Inoue ◽

Vasily Moshnyaga ◽

Kazuaki Murakami

Keyword(s):

Low Power ◽

Instruction Cache ◽

Cache Architecture

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