The increasing prominence of wireless multimedia systems and the need to limit power
capability in very-high density VLSI chips have led to rapid and innovative
developments in low-power design. Power reduction has emerged as a significant
design constraint in VLSI design. The need for wireless multimedia systems leads to
much higher power consumption than traditional portable applications. This paper
presents possible optimization technique to reduce the energy consumption for wireless
multimedia communication systems. Four topics are presented in the wireless
communication systems subsection which deal with architectures such as PN
acquisition, parallel correlator, matched filter and channel coding. Two topics include
the IDCT and motion estimation in multimedia application.These topics consider algorithms and architectures for low power design such as using
hybrid architecture in PN acquisition, analyzing the algorithm and optimizing the
sample storage in parallel correlator, using complex matched filter that analog
operational circuits controlled by digital signals, adopting bit serial arithmetic for the
ACS operation in viterbi decoder, using CRC to adaptively terminate the SOVA
iteration in turbo decoder, using codesign in RS codec, disabling the processing
elements as soon as the distortion values become great than the minimum distortion
value in motion estimation, and exploiting the relative occurrence of zero-valued DCT
coefficient in IDCT.