Low power instruction cache design based on branch execution tracks

2013 IEEE 10th International Conference on ASIC ◽

10.1109/asicon.2013.6811822 ◽

2013 ◽

Author(s):

Quanquan Li ◽

Qi Wang ◽

Tiejun Zhang ◽

Donghui Wang ◽

Chaohuan Hou

Keyword(s):

Low Power ◽

Instruction Cache ◽

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A Low-Power Instruction Cache Design Based on Record Buffer

Journal of Computer Research and Development ◽

10.1360/crad20060426 ◽

2006 ◽

Vol 43 (4) ◽

pp. 744

Author(s):

Zhiqiang Ma

Keyword(s):

Low Power ◽

Instruction Cache ◽

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An on-chip instruction cache design with one-bit tag for low-power embedded systems

Microprocessors and Microsystems ◽

10.1016/j.micpro.2011.02.003 ◽

2011 ◽

Vol 35 (4) ◽

pp. 382-391 ◽

Author(s):

Ji Gu ◽

Hui Guo ◽

Patrick Li

Keyword(s):

Embedded Systems ◽

Low Power ◽

Instruction Cache ◽

On Chip ◽

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Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.23919/date48585.2020.9116212 ◽

2020 ◽

Author(s):

Chen Jie ◽

Igor Loi ◽

Luca Benini ◽

Davide Rossi

Keyword(s):

Low Power ◽

Energy Efficient ◽

Ultra Low Power ◽

Instruction Cache ◽

Core Cluster ◽

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ROBTIC: An On-chip Instruction Cache Design for Low Power Embedded Systems

2009 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications ◽

10.1109/rtcsa.2009.51 ◽

2009 ◽

Author(s):

Ji Gu ◽

Hui Guo ◽

Patrick Li

Keyword(s):

Embedded Systems ◽

Low Power ◽

Instruction Cache ◽

On Chip ◽

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Low-Power Cache Design

Low-Power Electronics Design ◽

10.1201/9781420039559-32 ◽

2018 ◽

pp. 455-476

Keyword(s):

Low Power ◽

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First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption

Lecture Notes in Computer Science - Embedded Computer Systems: Architectures, Modeling, and Simulation ◽

10.1007/11512622_12 ◽

2005 ◽

pp. 103-111 ◽

Author(s):

Cheol Hong Kim ◽

Sunghoon Shim ◽

Jong Wook Kwak ◽

Sung Woo Chung ◽

Chu Shik Jhon

Keyword(s):

Energy Consumption ◽

Instruction Cache ◽

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Instruction cache design space exploration for embedded software applications

2015 19th International Symposium on VLSI Design and Test ◽

10.1109/isvdat.2015.7208127 ◽

2015 ◽

Author(s):

Rajendra Patel ◽

Arvind Rajawat

Keyword(s):

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Embedded Software ◽

Instruction Cache ◽

Software Applications ◽

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Cache Design for Low Power and High Yield

9th International Symposium on Quality Electronic Design (isqed 2008) ◽

10.1109/isqed.2008.4479707 ◽

2008 ◽

Author(s):

Baker Mohammad ◽

Martin Saint-Laurent ◽

Paul Bassett ◽

Jacob Abraham

Keyword(s):

Low Power ◽

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A compiler-controlled instruction cache architecture for an embedded low power microprocessor

The Fifth International Conference on Computer and Information Technology (CIT'05) ◽

10.1109/cit.2005.3 ◽

2005 ◽

Author(s):

Xiaoping Zhu ◽

T.T. Tay

Keyword(s):

Low Power ◽

Instruction Cache ◽

Cache Architecture

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Low Power Instruction Cache with Word Selective Line Buffer

2012 IEEE 15th International Conference on Computational Science and Engineering ◽

10.1109/iccse.2012.37 ◽

2012 ◽

Author(s):

Hyun-Bum Cho ◽

Ju-Hee Choi ◽

Seong-Tea Jhang ◽

Chu-Shik Jhon

Keyword(s):

Low Power ◽

Instruction Cache

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