An Adaptive Fault-Tolerant and Congestion Controlled Selection Strategy for On-chip Networks

2019 ◽  
Vol 09 ◽  
Author(s):  
Ashima Arora ◽  
Neeraj K Shukla ◽  
Shaloo Kikan
Keyword(s):  
Fault Tolerant ◽  
Selection Strategy ◽  
Transient Faults ◽  
Traffic Patterns ◽  
Feature Size ◽  
Communication Infrastructure ◽  
Networks On Chip ◽  
Measuring Network ◽  
Hardware Faults ◽  
On Chip

Networks on chip are being developed as a communication infrastructure in the design of Multiprocessor SOCs. With the reduction in feature size, transient faults on the links are becoming a major issue on the performance of NOCs. In this paper, two fault-tolerant algorithms are proposed. In the first algorithm, a faulty link tolerant algorithm is designed which by measuring network loads on the links will reduce transient faults and balances the load. To address the effect of hardware faults, fault and congestion controlled algorithm is designed that not only control the congestion, but also the faults on both links and the nodes. The proposed strategies are evaluated on two different synthetic traffic patterns and the results so obtained shows better network and hardware performance of both the routing in comparison with non-fault-tolerant routing.

A New Fault Tolerant Routing Algorithm for Networks on Chip

2019 ◽  
Vol 10 (3) ◽  
pp. 68-85
Author(s):  
Chakib Nehnouh ◽  
Mohamed Senouci
Keyword(s):  
Network Architecture ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Transient Faults ◽  
Networks On Chip ◽  
Congestion Detection ◽  
Novel Approach ◽  
On Chip ◽  
Detection Mechanisms ◽  
Correct Data

To provide correct data transmission and to handle the communication requirements, the routing algorithm should find a new path to steer packets from the source to the destination in a faulty network. Many solutions have been proposed to overcome faults in network-on-chips (NoCs). This article introduces a new fault-tolerant routing algorithm, to tolerate permanent and transient faults in NoCs. This solution called DINRA can satisfy simultaneously congestion avoidance and fault tolerance. In this work, a novel approach inspired by Catnap is proposed for NoCs using local and global congestion detection mechanisms with a hierarchical sub-network architecture. The evaluation (on reliability, latency and throughput) shows the effectiveness of this approach to improve the NoC performances compared to state of art. In addition, with the test module and fault register integrated in the basic architecture, the routers are able to detect faults dynamically and re-route packets to fault-free and congestion-free zones.

Performance of Gaussian and Non-Gaussian Synthetic Traffic on Networks-on-Chip

2017 ◽  
Vol 8 (2) ◽  
pp. 33-42 ◽  
Author(s):  
Amit Chaurasia ◽  
Vivek Kumar Sehgal
Keyword(s):  
Packet Loss ◽  
Marginal Distribution ◽  
Loss Probability ◽  
Multicore Architectures ◽  
Traffic Patterns ◽  
Networks On Chip ◽  
Real Time Traffic ◽  
Link Utilization ◽  
On Chip ◽  
Non Gaussian

In this paper, we have worked on the bursty synthetic traffic for Gaussian and Non-Gaussian traffic traces on the NoC architecture. This is the first study on the performance of Gaussian and Non-Gaussian application traffic on the multicore architectures. The real-time traffic having the marginal distribution are Non-Gaussian in nature, so any analytical studies or simulations will not be accurate, and does not capture the true characteristics of application traffic. Simulation is performed on synthetic generated traces for Gaussian and Non-Gaussian traffic for different traffic patterns. The performance of the two traffics is validated by simulating the parameters of packet loss-probability, average link-utilization & average end-to-end latency shows that the Non-Gaussian traffic captures the burstiness more effectively as compared to the Gaussian traffic for the desired application.

A Congestion Controlled and Load Balanced Selection Strategy for Networks on Chip

2020 ◽  
Vol 11 (1) ◽  
pp. 1-14
Author(s):  
Ashima Arora ◽  
Neeraj Kumar Shukla
Keyword(s):  
Traffic Flow ◽  
Free Path ◽  
Routing Algorithm ◽  
Experimental Results ◽  
Selection Strategy ◽  
Selection Function ◽  
Networks On Chip ◽  
Traffic Conditions ◽  
On Chip ◽  
Selection Of

For an on-chip router, the suitability of a particular routing algorithm relies on its selection of the best possible output paths. For representing congestion, the selection function of a routing algorithm uses an appropriate metric. The preferred selection metric will thus help in deciding the congested free path for any incoming flit. In this article, the fuzzy-based selection function is designed by using a cumulative flit count as a global metric of traffic estimation. The strategy provides an added advantage of effectively utilizing the links and thus regulates the traffic flow by keeping track of buffer usage and flits flow history simultaneously. The experimental results obtained under different traffic conditions, shows the proposed scheme outperforms other traditional, fuzzy based schemes in terms of both performance and power requirements.

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