Performance of Gaussian and Non-Gaussian Synthetic Traffic on Networks-on-Chip

2017 ◽  
Vol 8 (2) ◽  
pp. 33-42 ◽  
Author(s):  
Amit Chaurasia ◽  
Vivek Kumar Sehgal
Keyword(s):  
Packet Loss ◽  
Marginal Distribution ◽  
Loss Probability ◽  
Multicore Architectures ◽  
Traffic Patterns ◽  
Networks On Chip ◽  
Real Time Traffic ◽  
Link Utilization ◽  
On Chip ◽  
Non Gaussian

In this paper, we have worked on the bursty synthetic traffic for Gaussian and Non-Gaussian traffic traces on the NoC architecture. This is the first study on the performance of Gaussian and Non-Gaussian application traffic on the multicore architectures. The real-time traffic having the marginal distribution are Non-Gaussian in nature, so any analytical studies or simulations will not be accurate, and does not capture the true characteristics of application traffic. Simulation is performed on synthetic generated traces for Gaussian and Non-Gaussian traffic for different traffic patterns. The performance of the two traffics is validated by simulating the parameters of packet loss-probability, average link-utilization & average end-to-end latency shows that the Non-Gaussian traffic captures the burstiness more effectively as compared to the Gaussian traffic for the desired application.

Cluster Based Networks-on-Chip

2013 ◽  
Vol 4 (3) ◽  
pp. 25-41
Author(s):  
Khalid Latif ◽  
Amir-Mohammad Rahmani ◽  
Tiberiu Seceleanu ◽  
Hannu Tenhunen
Keyword(s):  
Critical Path ◽  
Network Interface ◽  
Path Delay ◽  
Traffic Patterns ◽  
Hop Count ◽  
Networks On Chip ◽  
Routing Strategy ◽  
Negative Exponential Distribution ◽  
On Chip ◽  
Negative Exponential

Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, the authors present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5×6 crossbar is used for the proposed architecture which requires one more 5×1 multiplexer without increasing the critical path delay of the router as compared to the 5×5 crossbar. The proposed router has been simulated for uniform, transpose and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead.

An Adaptive Fault-Tolerant and Congestion Controlled Selection Strategy for On-chip Networks

2019 ◽  
Vol 09 ◽  
Author(s):  
Ashima Arora ◽  
Neeraj K Shukla ◽  
Shaloo Kikan
Keyword(s):  
Fault Tolerant ◽  
Selection Strategy ◽  
Transient Faults ◽  
Traffic Patterns ◽  
Feature Size ◽  
Communication Infrastructure ◽  
Networks On Chip ◽  
Measuring Network ◽  
Hardware Faults ◽  
On Chip

Networks on chip are being developed as a communication infrastructure in the design of Multiprocessor SOCs. With the reduction in feature size, transient faults on the links are becoming a major issue on the performance of NOCs. In this paper, two fault-tolerant algorithms are proposed. In the first algorithm, a faulty link tolerant algorithm is designed which by measuring network loads on the links will reduce transient faults and balances the load. To address the effect of hardware faults, fault and congestion controlled algorithm is designed that not only control the congestion, but also the faults on both links and the nodes. The proposed strategies are evaluated on two different synthetic traffic patterns and the results so obtained shows better network and hardware performance of both the routing in comparison with non-fault-tolerant routing.

Special Issue on Networks-on-Chip and Memories for Multicore Architectures

2014 ◽  
Vol 38 (4) ◽  
pp. 253
Author(s):  
Diana Goehringer ◽  
Hamid Sarbazi-Azad ◽  
Rainer Stotzka
Keyword(s):  
Multicore Architectures ◽  
Special Issue ◽  
Networks On Chip ◽  
On Chip

scholarly journals In-channel misrouting suppression technique for deflection-routed networks on chip

2016 ◽  
Vol 29 (2) ◽  
pp. 309-323
Author(s):  
Igor Stojanovic ◽  
Goran Djordjevic
Keyword(s):  
Large Scale ◽  
Traffic Patterns ◽  
Networks On Chip ◽  
Area Efficiency ◽  
Network Load ◽  
Suppression Technique ◽  
Suppression Mechanism ◽  
On Chip ◽  
Large Scale Networks ◽  
The Cost

Deflection routing, where port-contentions in routers are resolved by intentionally misrouting some of packets along unwanted directions instead of storing them, has been proposed as a promising approach for improving power and area efficiency of large-scale networks on chip (NoCs). However, at high network load, when packets are misrouted more frequently, the cost and energy benefits of this simple routing scheme are offset by the performance degradation. To address this problem, we propose a technique that uses small in-channel buffers to capture some of deflected packets before they take a misrouting hop. The captured packets are then looped-back to the routers where they suffered deflection and routed again. To improve the efficiency of this in-channel misrouting suppression scheme we also slightly modify the routing function of the deflection router by restricting the choice of productive directions for misrouted packets. Evaluations on synthetic traffic patterns show that the proposed misrouting suppression mechanism yields an improvement of 36.2% in network saturation throughput when implemented into the conventional deflection-routed network.

Energy-Performance Analysis and Optimization for Networks-on-Chip

2014 ◽  
Vol 36 (5) ◽  
pp. 988-1003 ◽  
Author(s):  
Shuai ZHANG ◽  
Feng-Long SONG ◽  
Dong WANG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN
Keyword(s):  
Performance Analysis ◽  
Energy Performance ◽  
Networks On Chip ◽  
On Chip

scholarly journals Ray Tracing Modeling of Electromagnetic Propagation for On-Chip Wireless Optical Communications

2018 ◽  
Vol 8 (4) ◽  
pp. 39 ◽  
Author(s):  
Franco Fuschini ◽  
Marina Barbiroli ◽  
Marco Zoli ◽  
Gaetano Bellanca ◽  
Giovanna Calò ◽  
...  
Keyword(s):  
Ray Tracing ◽  
Path Loss ◽  
Wireless Channel ◽  
Electromagnetic Propagation ◽  
Networks On Chip ◽  
Spatial Properties ◽  
Radiation Properties ◽  
Wireless Optical Communications ◽  
On Chip ◽  
The Relationship

Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered as promising solutions to overcome the technological limits of wired interconnects. In this work, the spatial properties of the on-chip wireless channel are investigated through a ray tracing approach applied to a layered representation of the chip structure, highlighting the relationship between path loss, antenna positions and radiation properties.

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

Sign in / Sign up

Export Citation Format

Share Document