РАЗРАБОТКА ПРОТОТИПА ПРОГРАММНОГО МОДУЛЯ АВТОМАТИЗИРОВАННОЙ ГЕНЕРАЦИИ КВАЛИФИКАЦИОННЫХ ЯЧЕЕК ДЛЯ КОНТРОЛЯ ПРАВИЛ ПРОЕКТИРОВАНИЯ ИС

2020 ◽  
Vol 96 (3s) ◽  
pp. 721-725
Author(s):  
Ф.С. Золотухин ◽  
А.С. Надин ◽  
И.Е. Трифанихина
Keyword(s):  
Industrial Design ◽  
Automated Design ◽  
Design Rule ◽  
Software Module ◽  
The Real ◽  
Rule Checking ◽  
Design Rule Checking

Разработан прототип программного модуля генератора квалификационных ячеек для автоматизированного контроля геометрических правил проектирования DRC. Проведено тестирование прототипа генератора в реальных рабочих условиях проектирования. The paper presents a prototype of software module of the QA-cells Generator for automated Design Rule Checking. The QA-Cells Generator has been tested in the real workplace within actual microelectronic industrial design.

scholarly journals Design Rule Checking with a CNN Based Feature Extractor

2020 ◽  
Author(s):  
Luis Francisco ◽  
Tanmay Lagare ◽  
Arpit Jain ◽  
Somal Chaudhary ◽  
Madhura Kulkarni ◽  
...  
Keyword(s):  
Design Rule ◽  
Rule Checking ◽  
Feature Extractor ◽  
Design Rule Checking

Design Rule Checking

2018 ◽  
pp. 17-1-17-12
Author(s):  
Robert Todd ◽  
Laurence Grodd ◽  
Katherine Fetty
Keyword(s):  
Design Rule ◽  
Rule Checking ◽  
Design Rule Checking

Design Rule Checking

2016 ◽  
pp. 503-517
Author(s):  
Robert Todd ◽  
Laurence Grodd ◽  
Jimmy Tomblin ◽  
Katherine Fetty ◽  
Daniel Liddell
Keyword(s):  
Design Rule ◽  
Rule Checking ◽  
Design Rule Checking

scholarly journals Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment

VLSI Design ◽  
1994 ◽  
Vol 1 (2) ◽  
pp. 155-167
Author(s):  
S. K. Nandy
Keyword(s):  
Distributed Computing ◽  
Load Balancing ◽  
Geometric Design ◽  
Design Rule ◽  
Computing Environment ◽  
Rule Checking ◽  
Design Rule Checking ◽  
Spatial Independence

In this paper we provide a distributed solution to perform Design Rule Checking (DRC) of a layout by exploiting either spatial independence or layer independence in layout data. We show that the former approach to DRC can result in reasonable speedup only for large layouts, whereas, the latter approach shows a better performance for smaller layouts. We also provide an algorithm to optimally partition a layout and a scheme to allocate DRC tasks to idle processors in a Distributed Computing Environment (DCE) to attain load balancing.

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