Topologically rectangular grids offer simplicity and efficiency in the design of parallel semiconductor
device simulators tailored for mesh connected MIMD platforms. This paper
presents several approaches to the generation of topologically rectangular 2D and 3D grids.
The effects of the partitioning of such grids on different processor configurations are studied.
A simulated annealing algorithm is used to optimise the partitioning of 2D and 3D grids on
two dimensional arrays of processors. Problems related to the discretization, parallel matrix
generation and solution strategy are discussed. The use of topologically rectangular grids is
illustrated through the example of power electronic device simulation.