Improvement of Q rr-I DSS and dynamic avalanche of field-plate MOSFET by local lifetime control on the cathode side

Reducing the reverse recovery charge (Qrr) is effective for reducing switching loss in field plate (FP)-MOSFETs. A lifetime killer is utilized to reduce Qrr while increasing the leakage current in the off-state. Device simulation shows that a local lifetime killer on the cathode side successfully improves the trade-off between Qrr and IDSS in comparison with that of a uniform lifetime killer. A known issue of cathode lifetime killers is overshoot voltage by hard recovery. However, the overshoot voltage of FP-MOSFET decreases with a cathode lifetime killer owing to an internal snubber, which is a feature of FP-MOSFETs. An internal snubber with a large series resistance causes dynamic avalanche by both the increase of FP potential and excess carriers in high-speed operation. The cathode lifetime killer also improves dynamic avalanche by excess carriers. Consequently, the cathode lifetime killer is preferable for high-speed FP-MOSFETs.

The stress-strain state of the trailer seat-coupling device simulation

The article deals with the issues of modeling the stress-strain state of a traction device designed for towing a heavy semi-trailer, on which the equipment of the base station of a mobile transport and reloading rope complex is placed. The main design loads are defined. Geometric and computational finite element models are constructed, taking into account the features of the metal structure. The method of gluing elements of the grid model is applied. On the basis of the performed calculations, conclusions are drawn about the compliance of the developed structure with the requirements of strength.

Device Simulation of The GeSe Homojunction And vdW GeSe/GeTe Heterojunction TFETs For High-Performance Application

Compared with a 2D homogeneous channel, the introduction of a 2D/2D homojunction or heterojunction is a promising method to promote the performance of a TFET mainly by controlling the tunneling barrier. We simulate the 10-nm-Lg double-gated GeSe homojunction TFETs and vdW GeSe/GeTe heterojunction TFETs using the ab initio quantum transport calculations. Two constructions are considered for both the homojunction and heterojunction TFETs by placing the BL GeSe and vdW GeSe/GeTe heterojunction as the source or drain while the channel and the remaining drain or source use ML GeSe. The on-state current (Ion) of the optimal n-type BL-ML GeSe source homojunction TFET and the optimal p-type vdW GeSe/GeTe drain heterojunction TFET are 2320 and 2387 μA μm-1, respectively, which are 50% and 64% larger than Ion of the ML GeSe homogeneous TFET. Inspiringly, the device performances (Ion, intrinsic delay time τ, and power delay product PDP) of both the optimal n-type GeSe homojunction and p-type vdW GeSe/GeTe heterojunction TFETs meet the requirement of the International Roadmap for Device and Systems high-performance device for the year of 2034 (2020 version).