scholarly journals Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip

2020 ◽  
Author(s):  
Bo Wang ◽  
Jun Zhou ◽  
Weng-Fai Wong ◽  
Li-Shiuan Peh
Keyword(s):  
Low Power ◽  
Networks On Chip ◽  
Partial Sum ◽  
On Chip

scholarly journals Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip

2015 ◽  
Vol 11 (3) ◽  
pp. 552-566 ◽  
Author(s):  
Maurizio Palesi ◽  
Davide Patti ◽  
Giuseppe Ascia ◽  
Daniela Panno ◽  
Vincenzo Catania
Keyword(s):  
Low Power ◽  
Routing Algorithm ◽  
Power Networks ◽  
Networks On Chip ◽  
Data Encoding ◽  
On Chip

Asynchronous BFT for low power networks on chip

2010 ◽  
Author(s):  
Mohamed A. Abd El ghany ◽  
Magdy A. El-Moursy ◽  
Darek Korzec ◽  
Mohammed Ismail
Keyword(s):  
Low Power ◽  
Power Networks ◽  
Networks On Chip ◽  
On Chip

Low-Power Coding for Networks-on-Chip with Virtual Channels

2009 ◽  
Vol 5 (1) ◽  
pp. 77-84 ◽  
Author(s):  
Alberto García-Ortiz ◽  
Leandro S. Indrusiak ◽  
Tudor Murgan ◽  
Manfred Glesner
Keyword(s):  
Low Power ◽  
Networks On Chip ◽  
Virtual Channels ◽  
On Chip
Sign in / Sign up

Export Citation Format

Share Document