2009 IEEE Computer Society Annual Symposium on VLSI
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9781424444083

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A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient

2009 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2009.52 ◽

2009 ◽

Author(s):

Ravindhiran Mukundrajan ◽

Mrigank Sharma ◽

Badrinarayanan Ravi

Keyword(s):

High Performance ◽

Ground Plane ◽

Uniform Grid ◽

Voltage Gradient ◽

Plane Model ◽

The Impact ◽

Grid Based ◽

Heterogeneous Cores

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A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications

2009 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2009.51 ◽

2009 ◽

Cited By ~ 3

Author(s):

Sungmin Bae ◽

Krishnan Ramakrishnan ◽

Narayanan Vijaykrishnan

Keyword(s):

Low Power ◽

Low Area ◽

Fpga Architecture ◽

Area Overhead ◽

Body Bias

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High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect

2009 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2009.9 ◽

2009 ◽

Cited By ~ 1

Author(s):

Vijaya Sankara P. Rao ◽

Pradip Mandal ◽

Sunil Sachdev

Keyword(s):

High Speed

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Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation

2009 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2009.30 ◽

2009 ◽

Cited By ~ 5

Author(s):

Somayeh Timarchi ◽

Keivan Navi ◽

Omid Kavehei

Keyword(s):

High Radix

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High Performance Non-blocking Switch Design in 3D Die-Stacking Technology

2009 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2009.53 ◽

2009 ◽

Cited By ~ 7

Author(s):

Dean L. Lewis ◽

Sudhakar Yalamanchili ◽

Hsien-Hsin S. Lee

Keyword(s):

High Performance ◽

Die Stacking ◽

Switch Design

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All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex

2009 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2009.41 ◽

2009 ◽

Cited By ~ 2

Author(s):

Ramasahayam Swathi ◽

M.B. Srinivas

Keyword(s):

Duty Cycle

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[Cover art]

2009 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2009.60 ◽

2009 ◽

Keyword(s):

Cover Art

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A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits

2009 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2009.37 ◽

2009 ◽

Author(s):

Koustav Bhattacharya ◽

Nagarajan Ranganathan

Keyword(s):

Soft Errors ◽

Placement Algorithm

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Leakage Power and Side Channel Security of Nanoscale Cryptosystem-on-Chip (CoC)

2009 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2009.46 ◽

2009 ◽

Author(s):

Amir Khatib Zadeh ◽

Catherine Gebotys

Keyword(s):

Leakage Power ◽

Side Channel ◽

On Chip

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Publisher's Information

2009 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2009.56 ◽

2009 ◽

Download Full-text

2009 IEEE Computer Society Annual Symposium on VLSILatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient

A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications

High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect

Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation

High Performance Non-blocking Switch Design in 3D Die-Stacking Technology

All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex

[Cover art]

A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits

Leakage Power and Side Channel Security of Nanoscale Cryptosystem-on-Chip (CoC)

Publisher's Information

2009 IEEE Computer Society Annual Symposium on VLSI
Latest Publications