scholarly journals Verilog Implementation of Image Compression Using Discrete Wavelet Transform

2015 ◽  
Vol 9 (1) ◽  
pp. 21-25
Author(s):  
P. Sreekanth ◽  
Keyword(s):  
Wavelet Transform ◽  
Image Compression ◽  
Discrete Wavelet Transform ◽  
Discrete Wavelet

scholarly journals The optical image compression and encryption method based on Fresnel diffraction and discrete wavelet transform

2020 ◽  
Vol 1 ◽  
pp. 100021
Author(s):  
Chuhan Wu ◽  
Jun Chang ◽  
Chenggen Quan ◽  
Xiaofang Zhang ◽  
Yongjian Zhang
Keyword(s):  
Wavelet Transform ◽  
Image Compression ◽  
Discrete Wavelet Transform ◽  
Fresnel Diffraction ◽  
Optical Image ◽  
Discrete Wavelet ◽  
Encryption Method ◽  
Image Compression And Encryption

VLSI Architectures for Lifting Based Discrete Wavelet Transform – A Survey

2016 ◽  
Vol 3 (2) ◽  
pp. 323
Author(s):  
M. Kalaiarasi ◽  
T. Vigneswaran
Keyword(s):  
Wavelet Transform ◽  
Image Compression ◽  
Discrete Wavelet Transform ◽  
Video Compression ◽  
Perfect Reconstruction ◽  
Discrete Wavelet ◽  
Vlsi Architectures ◽  
3 Dimensional ◽  
Recursive Structures ◽  
Memory Power

<p>Image compression is a key technology in the development of various multimedia and communication applications. Perfect reconstruction of the image without any loss in picture quality and data is very important. This can be achieved with the Discrete Wavelet Transform (DWT), which is an efficient tool for image compression and video compression. The lifting based DWT architecture has the advantage of lower computational complexities and also requires less memory compared to the conventional convolution method. The existing DWT architectures are represented in terms of folded, flipping and recursive structures. The various architectures are discussed in terms of memory, power consumption and operating frequency involved with the given size of image and required levels of decomposition. This paper presents a survey of these architectures for 2-dimensional and 3-dimensional Discrete Wavelet Transform. This study is useful for deriving an efficient method for improving the speed and hardware complexities of existing architectures.</p>

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