scholarly journals A Study on Construction of the Advanced Sequential Circuit over Finite Fields

2019 ◽  
Vol 6 (4) ◽  
pp. 323-328
Author(s):  
Chun-Myoung Park
Author(s):  
Rudolf Lidl ◽  
Harald Niederreiter
Keyword(s):  

2018 ◽  
Vol 43 (1-4) ◽  
pp. 13-45
Author(s):  
Prof. P. L. Sharma ◽  
◽  
Mr. Arun Kumar ◽  
Mrs. Shalini Gupta ◽  
◽  
...  

2020 ◽  
Vol 25 (4) ◽  
pp. 4-9
Author(s):  
Yerzhan R. Baissalov ◽  
Ulan Dauyl

The article discusses primitive, linear three-pass protocols, as well as three-pass protocols on associative structures. The linear three-pass protocols over finite fields and the three-pass protocols based on matrix algebras are shown to be cryptographically weak.


Vestnik MEI ◽  
2018 ◽  
Vol 5 (5) ◽  
pp. 79-88
Author(s):  
Sergey B. Gashkov ◽  
◽  
Aleksandr B. Frolov ◽  
Elizaveta Р. Popova ◽  
◽  
...  

Author(s):  
Anna ILYENKO ◽  
Sergii ILYENKO ◽  
Yana MASUR

In this article, the main problems underlying the current asymmetric crypto algorithms for the formation and verification of electronic-digital signature are considered: problems of factorization of large integers and problems of discrete logarithm. It is noted that for the second problem, it is possible to use algebraic groups of points other than finite fields. The group of points of the elliptical curve, which satisfies all set requirements, looked attractive on this side. Aspects of the application of elliptic curves in cryptography and the possibilities offered by these algebraic groups in terms of computational efficiency and crypto-stability of algorithms were also considered. Information systems using elliptic curves, the keys have a shorter length than the algorithms above the finite fields. Theoretical directions of improvement of procedure of formation and verification of electronic-digital signature with the possibility of ensuring the integrity and confidentiality of information were considered. The proposed method is based on the Schnorr signature algorithm, which allows data to be recovered directly from the signature itself, similarly to RSA-like signature systems, and the amount of recoverable information is variable depending on the information message. As a result, the length of the signature itself, which is equal to the sum of the length of the end field over which the elliptic curve is determined, and the artificial excess redundancy provided to the hidden message was achieved.


Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.


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