Analytical Gate Delay Variation Model with Temperature Effects in Near-Threshold Region Based on Log-Skew-Normal Distribution

The near-threshold design is widely employed in the energy-efficient circuits, but it suffers from a high sensitivity to process variation, which leads to 2X delay variation due to temperature effects. Hence, it is not negligible. In this paper, we propose an analytical model for gate delay variation considering temperature effects in the near-threshold region. The delay variation model is constructed based on the log-skew-normal distribution by moment matching. Moreover, to deal with complex gates, a multi-variate threshold voltage approximation approach of stacked transistors is proposed. Also, three delay metrics (delay variability, ± 3 σ percentile points) are quantified and have a comparison with other known works. Experimental results show that the maximum of delay variability is 5% compared with Monte Carlo simulation and improves 5X in stacked gates compared with lognormal distribution. Additionally, it is worth mentioning that, the proposed model exhibits excellent advantages on − 3 σ and stacked gates, which improves 5X–10X in accuracy compared with other works.