Experimental Review of ΛΛ¯ Production

Exclusive hyperon-antihyperon production provides a unique insight for understanding of the intrinsic dynamics when strangeness is involved. In this paper, we review the results of ΛΛ¯ production via different reactions from various experiments, e.g., via p¯p annihilation from the LEAR experiment PS185, via electron-positron annihilation using the energy scan method at the CLEO-c and BESIII experiments and the initial-state-radiation approach utilized at the BaBar experiment. The production cross section of ΛΛ¯ near the threshold is sensitive to QCD based prediction. Experimental high precision data for p¯p→Λ¯Λ close to the threshold region is obtained. The cross section of e+e−→ΛΛ¯ is measured from its production threshold to high energy. A non-zero cross section for e+e−→ΛΛ¯ near threshold is observed at BaBar and BESIII, which is in disagreement with the pQCD prediction. However, more precise data is needed to confirm this observation. Future experiments, utilizing p¯p reaction such as PANDA experiment or electron-positron annihilation such as the BESIII and BelleII experiments, are needed to extend the experimental data and to understand the ΛΛ¯ production.

Compact and Energy Efficient Neuron With Tunable Spiking Frequency in 22-nm FDSOI

In this paper, we present a mixed-signal integrate and fire neuron designed in a 22-nm FDSOI technology. In this novel design, we deploy the back-gate terminal of FDSOI technology for a tunable design. For the first time, we show analytically and with pre- and post-layout simulations a neuron with tunable spiking frequency using the back-gate voltage of FDSOI technology. The neuron circuit is designed in the sub-threshold region and dissipates an ultra-low energy per spike of the order of Femto Joules per spike. With the layout area of only 30um^2, this is the smallest neuron circuit reported to date.

Compact and Energy Efficient Neuron With Tunable Spiking Frequency in 22-nm FDSOI

In this paper, we present a mixed-signal integrate and fire neuron designed in a 22-nm FDSOI technology. In this novel design, we deploy the back-gate terminal of FDSOI technology for a tunable design. For the first time, we show analytically and with pre- and post-layout simulations a neuron with tunable spiking frequency using the back-gate voltage of FDSOI technology. The neuron circuit is designed in the sub-threshold region and dissipates an ultra-low energy per spike of the order of Femto Joules per spike. With the layout area of only 30um^2, this is the smallest neuron circuit reported to date.

A STUDY ON THE RELATION BETWEEN MORPHOLOGICAL AND CHEMICAL CHANGES AND WETTABILITY MODIFICATION OF POLYETHERSULFONE SURFACE AFTER IRRADIATION WITH A PULSED KrF LASER

Laser irradiation is used for surface modification of polymers aiming to improve their properties for different applications. The wettability of a polymeric surface can significantly affect its performance for biological applications. In this paper, the interaction of high-energy KrF laser photons in the two above- and below-threshold regimes with polyethersulfone polymer is studied. The role of morphological and chemical changes of the irradiated polymer and their correlation in the modification of the wetting property of this polymer is investigated. The obtained results show that the morphological parameter of surface roughness is the dominant mechanism in the below-threshold regime, while in the above-threshold region, the competition between this parameter and the carbonization amount of the surface determines the final hydrophilic response.

Transport Triggered Array Processor for Vision Applications: Near-threshold Performance Loss Compensation Through Inherent Parallelism of Vision Array Processors

<div>Operating at reduced voltages promises substantial energy efficiency improvement, however the downside is significant down-scaling of clock frequency. This paper propose vision chips as excellent fit for low-voltage operation. Low-level sensory data processing in many Internet-of-Things (IoT) devices pursue energy efficiency by utilizing sleep modes or slowing the clocking to the minimum. To curb the share of stand-by power dissipation in those designs, near-threshold/sub-threshold operational points or ultra-low-leakage processes in fabrication are employed. Those limit the clocking rates significantly, reducing the computing throughputs of individual processing cores. In this contribution we explore compensating for the performance loss of operating in near-threshold region ($V_{dd}=$0.6V) through massive parallelization. Benefits of near-threshold operation and massive parallelism are optimum energy consumption per instruction operation and minimized memory round-trips, respectively. The Processing Elements (PE) of the design are based on Transport Triggered Architecture. The fine grained programmable parallel solution allows for fast and efficient computation of learnable low-level features (e.g. local binary descriptors and convolutions). Other operations, including Max-pooling have also been implemented. The programmable design achieves excellent energy efficiency for Local Binary Patterns computations. </div><div>Our results demonstrates that the inherent properties of chip processor and vision applications allow voltage and clock frequency aggressively without having to compromise performance. </div>

Transport Triggered Array Processor for Vision Applications: Near-threshold Performance Loss Compensation Through Inherent Parallelism of Vision Array Processors

<div>Operating at reduced voltages promises substantial energy efficiency improvement, however the downside is significant down-scaling of clock frequency. This paper propose vision chips as excellent fit for low-voltage operation. Low-level sensory data processing in many Internet-of-Things (IoT) devices pursue energy efficiency by utilizing sleep modes or slowing the clocking to the minimum. To curb the share of stand-by power dissipation in those designs, near-threshold/sub-threshold operational points or ultra-low-leakage processes in fabrication are employed. Those limit the clocking rates significantly, reducing the computing throughputs of individual processing cores. In this contribution we explore compensating for the performance loss of operating in near-threshold region ($V_{dd}=$0.6V) through massive parallelization. Benefits of near-threshold operation and massive parallelism are optimum energy consumption per instruction operation and minimized memory round-trips, respectively. The Processing Elements (PE) of the design are based on Transport Triggered Architecture. The fine grained programmable parallel solution allows for fast and efficient computation of learnable low-level features (e.g. local binary descriptors and convolutions). Other operations, including Max-pooling have also been implemented. The programmable design achieves excellent energy efficiency for Local Binary Patterns computations. </div><div>Our results demonstrates that the inherent properties of chip processor and vision applications allow voltage and clock frequency aggressively without having to compromise performance. </div>

Analog/RF Performance of Triple Material Gate Stack-Graded Channel Double Gate-Junctionless Strained-Silicon MOSFET with Fixed Charges

In this paper, analog/radio frequency (RF) electrical characteristics of triple material gate stackgraded channel double gate-Junctionless (TMGS-GCDGJL) strained-Si (s-Si) MOSFET with fixed charge density is analyzed with the help of Sentaurus TCAD. By varying the various device parameters, the analog/RF performance of the proposed TMGS-GCDG-JL s-Si MOSFET is evaluated in terms of transconductance-generationfactor (TGF), early voltage, voltage gain, unity-powergain frequency ( f max ), unity-current-gain frequency ( f t ), and gain-transconductance frequency product (GTFP). The results confirm that the proposed TMGS-GCDGJL s-Si MOSFET has superior analog/RF performance compared to gate stack-graded channel double gatejunctionless (GS-GCDG-JL) s-Si device. However, the proposed MOSFET has less transconductance and less output conductance when compared with the GS-GCDGJL s-Si device in above threshold region, and reverse trend follows in sub-threshold region.

Design of Low Leakage 9T SRAM Cell with -Low Power Devices

In this paper, a 9T SRAM cell with low power (LP9T) and improved performance has been proposed. This cell is free from half-select issue and works with single-ended read and differential write operation in the sub-threshold region. To evaluate the relative performance, the obtained characteristics of LP9T SRAM cell are compared with other state-of-the-art designs at 45-nm technology node. The read and write power dissipation of LP9T SRAM cell is reduced by [Formula: see text] and [Formula: see text] as compared to Conv.6T SRAM cell. In proposed cell, leakage power is reduced by [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text] and [Formula: see text] as compared to conventional 6T (Conv.6T), low power (LP8T), transmission gate 8T(TG8T), transmission gate 9T (TG9T), Schmitt trigger 9T (ST9T), and positive feedback control 10T (PFC10T) SRAM cells. This reduction in leakage power is attributed to stacking effect. LP9T SRAM cell also exhibits significant improvement in read/write access time as compared to all considered cells. Also, the read and write energy of proposed cell is lowest among all considered cells. The LP9T SRAM cell has [Formula: see text] and [Formula: see text] higher read and write stability as compared to Conv.6T SRAM cell. Proposed SRAM cell has the highest value of ON to OFF current ratio ([Formula: see text]) which signifies the highest bit-cell density among all considered cells. The LP9T SRAM cell occupies [Formula: see text] large area as compared to Conv.6T SRAM cell. The overall quality of SRAM cell is calculated through the electrical quality metric (EQM). It is observed that LP9T SRAM cell has the highest value of EQM in comparison to considered cells at 0.3[Formula: see text]V supply voltage.

Topological analysis of interaction patterns in cancer-specific gene regulatory network: persistent homology approach

In this study, we investigated cancer cellular networks in the context of gene interactions and their associated patterns in order to recognize the structural features underlying this disease. We aim to propose that the quest of understanding cancer takes us beyond pairwise interactions between genes to a higher-order construction. We characterize the most prominent network deviations in the gene interaction patterns between cancer and normal samples that contribute to the complexity of this disease. What we hope is that through understanding these interaction patterns we will notice a deeper structure in the cancer network. This study uncovers the significant deviations that topological features in cancerous cells show from the healthy one, where the last stage of filtration confirms the importance of one-dimensional holes (topological loops) in cancerous cells and two-dimensional holes (topological voids) in healthy cells. In the small threshold region, the drop in the number of connected components of the cancer network, along with the rise in the number of loops and voids, all occurring at some smaller weight values compared to the normal case, reveals the cancerous network tendency to certain pathways.