Evaluation of access patterns from log Ontology with DL-safe rules

2009 ◽  
Vol 29 (5) ◽  
pp. 1401-1404
Author(s):  
Ming SUN ◽  
Bo CHEN ◽  
Ming-tian ZHOU
Keyword(s):  
Access Patterns

scholarly journals Machine Learning–enabled Scalable Performance Prediction of Scientific Codes

2021 ◽  
Vol 31 (2) ◽  
pp. 1-28
Author(s):  
Gopinath Chennupati ◽  
Nandakishore Santhi ◽  
Phill Romero ◽  
Stephan Eidenbenz
Keyword(s):  
Machine Learning ◽  
Performance Prediction ◽  
Prediction Models ◽  
Radiation Transport ◽  
Discrete Event ◽  
Basic Block ◽  
Distribution Models ◽  
Scientific Application ◽  
High Level ◽  
Access Patterns

Hardware architectures become increasingly complex as the compute capabilities grow to exascale. We present the Analytical Memory Model with Pipelines (AMMP) of the Performance Prediction Toolkit (PPT). PPT-AMMP takes high-level source code and hardware architecture parameters as input and predicts runtime of that code on the target hardware platform, which is defined in the input parameters. PPT-AMMP transforms the code to an (architecture-independent) intermediate representation, then (i) analyzes the basic block structure of the code, (ii) processes architecture-independent virtual memory access patterns that it uses to build memory reuse distance distribution models for each basic block, and (iii) runs detailed basic-block level simulations to determine hardware pipeline usage. PPT-AMMP uses machine learning and regression techniques to build the prediction models based on small instances of the input code, then integrates into a higher-order discrete-event simulation model of PPT running on Simian PDES engine. We validate PPT-AMMP on four standard computational physics benchmarks and present a use case of hardware parameter sensitivity analysis to identify bottleneck hardware resources on different code inputs. We further extend PPT-AMMP to predict the performance of a scientific application code, namely, the radiation transport mini-app SNAP. To this end, we analyze multi-variate regression models that accurately predict the reuse profiles and the basic block counts. We validate predicted SNAP runtimes against actual measured times.

scholarly journals Realistic Aspects of Simulation Models for Fake News Epidemics over Social Networks

2021 ◽  
Vol 13 (3) ◽  
pp. 76
Author(s):  
Quintino Francesco Lotito ◽  
Davide Zanella ◽  
Paolo Casari
Keyword(s):  
Social Networks ◽  
Online Social Networks ◽  
Simulation Models ◽  
Epidemic Models ◽  
Time Varying ◽  
Fake News ◽  
Network Access ◽  
Spreading Process ◽  
Network Topologies ◽  
Access Patterns

The pervasiveness of online social networks has reshaped the way people access information. Online social networks make it common for users to inform themselves online and share news among their peers, but also favor the spreading of both reliable and fake news alike. Because fake news may have a profound impact on the society at large, realistically simulating their spreading process helps evaluate the most effective countermeasures to adopt. It is customary to model the spreading of fake news via the same epidemic models used for common diseases; however, these models often miss concepts and dynamics that are peculiar to fake news spreading. In this paper, we fill this gap by enriching typical epidemic models for fake news spreading with network topologies and dynamics that are typical of realistic social networks. Specifically, we introduce agents with the role of influencers and bots in the model and consider the effects of dynamical network access patterns, time-varying engagement, and different degrees of trust in the sources of circulating information. These factors concur with making the simulations more realistic. Among other results, we show that influencers that share fake news help the spreading process reach nodes that would otherwise remain unaffected. Moreover, we emphasize that bots dramatically speed up the spreading process and that time-varying engagement and network access change the effectiveness of fake news spreading.

scholarly journals Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures

2010 ◽  
Vol 2010 ◽  
pp. 1-16 ◽  
Author(s):  
James Coole ◽  
Greg Stitt
Keyword(s):  
Data Structures ◽  
Reconfigurable Computing ◽  
Application Development ◽  
Sequential Memory ◽  
Generalized Framework ◽  
Field Programmable ◽  
Order Of Magnitude ◽  
Programmable Gate Arrays ◽  
Irregular Data ◽  
Access Patterns

Field-programmable gate arrays (FPGAs) and other reconfigurable computing (RC) devices have been widely shown to have numerous advantages including order of magnitude performance and power improvements compared to microprocessors for some applications. Unfortunately, FPGA usage has largely been limited to applications exhibiting sequential memory access patterns, thereby prohibiting acceleration of important applications with irregular patterns (e.g., pointer-based data structures). In this paper, we present a design pattern for RC application development that serializes irregular data structure traversals online into a traversal cache, which allows the corresponding data to be efficiently streamed to the FPGA. The paper presents a generalized framework that benefits applications with repeated traversals, which we show can achieve between 7x and 29x speedup over pointer-based software. For applications without strictly repeated traversals, we present application-specialized extensions that benefit applications with highly similar traversals by exploiting similarity to improve memory bandwidth and execute multiple traversals in parallel. We show that these extensions can achieve a speedup between 11x and 70x on a Virtex4 LX100 for Barnes-Hut n-body simulation.

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