HARDWARE IMPLEMENTATION OF VIDEO PROCESSING DEVICE USING RESIDUE NUMBER SYSTEM

2021 ◽  
pp. 15-21
Author(s):  
Pavel Alekseyevich Lyakhov ◽  
Andrey Sergeevich Ionisyan ◽  
Violetta Vladimirovna Masaeva ◽  
Maria Vasilevna Valueva
Keyword(s):  
Video Processing ◽  
Hardware Implementation ◽  
Number System ◽  
Residue Number System ◽  
Residue Number ◽  
Processing Device

An improved hardware implementation of the one hot Residue Number System

2014 ◽  
Author(s):  
Carlos Arturo Gayoso ◽  
Claudio Gonzalez ◽  
Leonardo Arnone ◽  
Miguel Rabini ◽  
Jorge Castineira Moreira
Keyword(s):  
Hardware Implementation ◽  
Number System ◽  
Residue Number System ◽  
Residue Number ◽  
The One

scholarly journals Data Flow Oriented Hardware Design of RNS-based Polynomial Multiplication for SHE Acceleration

2018 ◽  
pp. 69-88
Author(s):  
Joël Cathébras ◽  
Alexandre Carbon ◽  
Peter Milder ◽  
Renaud Sirdey ◽  
Nicolas Ventroux
Keyword(s):  
Hardware Implementation ◽  
Computation Time ◽  
Number System ◽  
Residue Number System ◽  
Polynomial Multiplication ◽  
Basis Size ◽  
Residue Number ◽  
Speed Up ◽  
Channel Dependent ◽  
Reasonable Use

This paper presents a hardware implementation of a Residue Polynomial Multiplier (RPM), designed to accelerate the full Residue Number System (RNS) variant of the Fan-Vercauteren scheme proposed by Bajard et al. [BEHZ16]. Our design speeds up polynomial multiplication via a Negative Wrapped Convolution (NWC) which locally computes the required RNS channel dependent twiddle factors. Compared to related works, this design is more versatile regarding the addressable parameter sets for the BFV scheme. This is mainly brought by our proposed twiddle factor generator that makes the design BRAM utilization independent of the RNS basis size, with a negligible communication bandwidth usage for non-payload data. Furthermore, the generalization of a DFT hardware generator is explored in order to generate RNS friendly NTT architectures. This approach helps us to validate our RPM design over parameter sets from the work of Halevi et al. [HPS18]. For the depth-20 setting, we achieve an estimated speed up for the residue polynomial multiplications greater than 76 during ciphertexts multiplication, and greater than 16 during relinearization. It thus results in a single-threaded Mult&Relin ciphertext operation in 109.4 ms (×3.19 faster than [HPS18]) with RPM counting for less than 15% of the new computation time. Our RPM design scales up with reasonable use of hardware resources and realistic bandwidth requirements. It can also be exploited for other RNS based implementations of RLWE cryptosystems.

scholarly journals Hardware implementation of a convolutional neural network using calculations in the residue number system

2019 ◽  
Vol 43 (5) ◽  
pp. 857-868 ◽  
Author(s):  
N.I. Chervyakov ◽  
P.A. Lyakhov ◽  
N.N. Nagornov ◽  
M.V. Valueva ◽  
G.V. Valuev
Keyword(s):  
Neural Network ◽  
Convolutional Neural Network ◽  
Network Architecture ◽  
Hardware Implementation ◽  
Traditional Approach ◽  
Number System ◽  
Residue Number System ◽  
Quantization Noise ◽  
The Neural Network ◽  
Residue Number

Modern convolutional neural networks architectures are very resource intensive which limits the possibilities for their wide practical application. We propose a convolutional neural network architecture in which the neural network is divided into hardware and software parts to increase performance and reduce the cost of implementation resources. We also propose to use the residue number system in the hardware part to implement the convolutional layer of the neural network for resource costs reducing. A numerical method for quantizing the filters coefficients of a convolutional network layer is proposed to minimize the influence of quantization noise on the calculation result in the residue number system and determine the bit-width of the filters coefficients. This method is based on scaling the coefficients by a fixed number of bits and rounding up and down. The operations used make it possible to reduce resources in hardware implementation due to the simplifying of their execution. All calculations in the convolutional layer are performed on numbers in a fixed-point format. Software simulations using Matlab 2017b showed that convolutional neural network with a minimum number of layers can be quickly and successfully trained. Hardware implementation using the field-programmable gate array Kintex7 xc7k70tfbg484-2 showed that the use of residue number system in the convolutional layer of the neural network reduces the hardware costs by 32.6% compared with the traditional approach based on the two’s complement representation. The research results can be applied to create effective video surveillance systems, for recognizing handwriting, individuals, objects and terrain.

High Performance Digital Filtering on Modified Multiply and Accumulate Unit in Residue Number System with Special Type of Moduli

2021 ◽  
Vol 27 (4) ◽  
pp. 171-179
Author(s):  
P. A. Lyakhov ◽  
◽  
A. S. Ionisyan ◽  
M. V. Valueva ◽  
A. S. Larikova ◽  
...  
Keyword(s):  
High Performance ◽  
Digital Filters ◽  
Hardware Implementation ◽  
Digital Filtering ◽  
Number System ◽  
Residue Number System ◽  
Residue Number ◽  
Simulation Results ◽  
Hardware Costs ◽  
Positional Number System

The paper proposes the implementation of digital filtering using residue number system and the modified truncated multiply and accumulate unit. The work was carried out a theoretical analysis of digital filters using residue number system arithmetic and implemented hardware simulation on FPGA. FPGA hardware simulation results show that the use of residue number system allows to increase the frequency of digital filters up to about 4 times and hardware costs reduce up to 3 times compared to using a common positional number system. The obtained results open up the possibility for efficient hardware implementation of digital filters on modern devices (FPGA, ASIC and etc.) to solve practical problems, such as noise reduction, amplification and suppression of the frequency spectrum, interpolation, decimation, equalization and many others.

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