scholarly journals Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2 m ) for Irreducible Polynomials

ETRI Journal ◽  
2017 ◽  
Vol 39 (4) ◽  
pp. 570-581 ◽  
Author(s):  
Sudha Ellison Mathe ◽  
Lakshmi Boppana
2016 ◽  
Vol 2016 ◽  
pp. 1-6
Author(s):  
Jiantao Wang ◽  
Dong Zheng ◽  
Zheng Huang

In the Galois fieldsGF(2n), a polynomial basis with a small number of trace-one elements is desirable for its convenience in computing. To find new irreducible polynomialsg(x)overGF(2)with this property, we research into the auxiliary polynomialf(x)=(x+1)g(x)with roots{1,α1,α2,…,αn}, such that the symmetric polynomialssk=1+α1k+α2k+⋯+αnkare relative to the symmetric polynomials ofg(x). We introduce a new class of polynomials with the number “1” occupying most of the values in itssk. This indicates that the number “0” occupies most of the values of the traces of the elements{α1,α2,…,αn}. This new class of polynomial gives us an indirect way to find irreducible polynomials having a small number of trace-one elements in their polynomial bases.


This paper presents a high speed low power systolic multiplier based on irreducible trinomials which is implemented using GF (2M). To calculate a set of d partial products in each Handling Element (HE) during every cycle we suggest multiplication algorithm of digit level. By using the systolic channels independently, operands in the proposed structure will be reduced and accumulated by partial products. Functional verification (Simulation) of the multiplier is done by using Xilinx ISE and synthesis is done by using Xilinx XST. The synthesized design is implemented on Zynq7000 FPGA. After completion of the synthesis, it is found that the proposed multiplier achieved power consumption of 2.9mW. Area and the performance of the multiplier is optimized in the proposed structures.


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