System-on-Chip Design Using High-Level Synthesis Tools

Erdal Oruklu; Richard Hanley; Semih Aslan; Christophe Desmouliers; Fernando M. Vallina; Jafar Saniie

doi:10.4236/cs.2012.31001

System-on-Chip Design Using High-Level Synthesis Tools

Circuits and Systems ◽

10.4236/cs.2012.31001 ◽

2012 ◽

Vol 03 (01) ◽

pp. 1-9 ◽

Cited By ~ 7

Author(s):

Erdal Oruklu ◽

Richard Hanley ◽

Semih Aslan ◽

Christophe Desmouliers ◽

Fernando M. Vallina ◽

...

Keyword(s):

System On Chip ◽

High Level Synthesis ◽

Chip Design ◽

On Chip ◽

High Level

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System on Chip Design with Vivado High-Level Synthesis Tool

2019 11th International Conference on Electrical and Electronics Engineering (ELECO) ◽

10.23919/eleco47770.2019.8990595 ◽

2019 ◽

Author(s):

Bans Bilgili ◽

Ceyhun Yamaneren ◽

Kubilay Vatansever ◽

Umut Coltu ◽

Bema Ors

Keyword(s):

System On Chip ◽

High Level Synthesis ◽

Chip Design ◽

Synthesis Tool ◽

On Chip ◽

High Level

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High Level System-on-Chip Design using UML and SystemC

Electronics, Robotics and Automotive Mechanics Conference (CERMA 2007) ◽

10.1109/cerma.2007.4367776 ◽

2007 ◽

Cited By ~ 1

Author(s):

Blanca Alicia Correa ◽

Juan Fernando Eusse ◽

Danny Munera ◽

Jose Edinson Aedo ◽

Juan Fernando Velez

Keyword(s):

System On Chip ◽

Level System ◽

Chip Design ◽

On Chip ◽

High Level

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Multidimensional representation of ultrasonic data processed by Reconfigurable Ultrasonic System-on-Chip using OpenCL high-level synthesis

2014 IEEE International Ultrasonics Symposium ◽

10.1109/ultsym.2014.0481 ◽

2014 ◽

Cited By ~ 4

Author(s):

Spenser Gilliland ◽

Clementine Boulet ◽

Thomas Gonnot ◽

Jafar Saniie

Keyword(s):

System On Chip ◽

High Level Synthesis ◽

On Chip ◽

High Level ◽

Multidimensional Representation

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A Framework for High-Level Synthesis of System-on-Chip Designs

2005 IEEE International Conference on Microelectronic Systems Education (MSE'05) ◽

10.1109/mse.2005.8 ◽

2006 ◽

Cited By ~ 29

Author(s):

J.E. Stine ◽

J. Grad ◽

I. Castellanos ◽

J. Blank ◽

V. Dave ◽

...

Keyword(s):

System On Chip ◽

High Level Synthesis ◽

On Chip ◽

High Level

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Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool

Communications in Computer and Information Science - Applied Computer Sciences in Engineering ◽

10.1007/978-3-030-31019-6_5 ◽

2019 ◽

pp. 52-63

Author(s):

Luis Castano-Londono ◽

Cristian Alzate Anzola ◽

David Marquez-Viloria ◽

Guillermo Gallo ◽

Gustavo Osorio

Keyword(s):

System On Chip ◽

High Level Synthesis ◽

Synthesis Tool ◽

On Chip ◽

High Level ◽

Algorithm Parallelization

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Study of System-on-Chip devices to implement embedded real-time simulators of modular multi-level converters using high-level synthesis tools

2018 IEEE International Conference on Industrial Technology (ICIT) ◽

10.1109/icit.2018.8352393 ◽

2018 ◽

Cited By ~ 2

Author(s):

D. Tormo ◽

R. Vidal-Albalate ◽

L. Idkhajine ◽

E. Monmasson ◽

R. Blasco-Gimenez

Keyword(s):

Real Time ◽

System On Chip ◽

High Level Synthesis ◽

Multi Level ◽

On Chip ◽

High Level

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Developing silicon intellectual property E-trade mechanisms for system on chip design and integration

International Journal of Computer Integrated Manufacturing ◽

10.1080/09511920601160122 ◽

2007 ◽

Vol 20 (5) ◽

pp. 423-435 ◽

Cited By ~ 1

Author(s):

C. V. Trappey ◽

A. J. C. Trappey ◽

F. T. L. Lin

Keyword(s):

Intellectual Property ◽

System On Chip ◽

Chip Design ◽

On Chip

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Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design

2012 25th International Conference on VLSI Design ◽

10.1109/vlsid.2012.31 ◽

2012 ◽

Cited By ~ 1

Author(s):

Susmita Sur-Kolay ◽

S. Bhunia

Keyword(s):

Intellectual Property ◽

System On Chip ◽

Intellectual Property Protection ◽

Chip Design ◽

On Chip

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System Architecting and System-on-Chip Design of Intelligent Sensor Networks for Active Volcanoes

2008 2nd Annual IEEE Systems Conference ◽

10.1109/systems.2008.4519025 ◽

2008 ◽

Cited By ~ 2

Author(s):

Wai-Chi Fang ◽

Sharon Kedar

Keyword(s):

Sensor Networks ◽

System On Chip ◽

Chip Design ◽

Intelligent Sensor ◽

On Chip ◽

Intelligent Sensor Networks ◽

Active Volcanoes

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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

10.1007/978-981-10-1073-6 ◽

2018 ◽

Author(s):

Zheng Wang ◽

Anupam Chattopadhyay

Keyword(s):

System On Chip ◽

High Level Estimation ◽

On Chip ◽

High Level

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