Parallel Hybrid Particle Swarm Algorithm for Workshop Scheduling Based on Spark

In hybrid mixed-flow workshop scheduling, there are problems such as mass production, mass manufacturing, mass assembly and mass synthesis of products. In order to solve these problems, combined with the Spark platform, a hybrid particle swarm algorithm that will be parallelized is proposed. Compared with the existing intelligent algorithms, the parallel hybrid particle swarm algorithm is more conducive to the realization of the global optimal solution. In the loader manufacturing workshop, the optimization goal is to minimize the maximum completion time and a parallelized hybrid particle swarm algorithm is used. The results show that in the case of relatively large batches, the parallel hybrid particle swarm algorithm can effectively obtain the scheduling plan and avoid falling into the local optimal solution. Compared with algorithm serialization, algorithm parallelization improves algorithm efficiency by 2–4 times. The larger the batches, the more obvious the algorithm parallelization improves computational efficiency.

Analysis and architecture design of scalable fractional motion estimation for H.264 encoding

FractionalMotion Estimation (FME) is an important part of the H.264/AVC video encoding standard. FME can significantly increase the compression ratio achievable by video encoders while improving video quality. However, it is computationally expensive and can consist of over 45% of the total motion estimation runtime. To maximize the performance and hardware utilization of FME implementations on Field-Programmable Gate Arrays (FGPAs), one needs to effectively exploit the inherent parallelism in an algorithm. In the work we explore two approaches to FME algorithm parallelization in order to effectively increase the processing power of the computing hardware. The first method is referred to as vertical scaling and the second horizontal scaling. In total, we implemented six scaled FME designs on a Xilinx Virtex-5 FPGA. We found that our best scaled FME design exhibited a speedup of 8x over the horizontally scaled designs. Additionally, we conclude that scaling vertically within 4x4 pixel sub-block is more efficient than scaling horizontally across several sub-blocks. As a result we were able to achieve higher video resolutions at lower resource costs. In particular, it is shown that the best vertically scaled design can achieve 30 fps of QSXGA (2560x2048) video using 4 reference frames with only 25.5L LUTS and 28.7K registers.

Analysis and architecture design of scalable fractional motion estimation for H.264 encoding

FractionalMotion Estimation (FME) is an important part of the H.264/AVC video encoding standard. FME can significantly increase the compression ratio achievable by video encoders while improving video quality. However, it is computationally expensive and can consist of over 45% of the total motion estimation runtime. To maximize the performance and hardware utilization of FME implementations on Field-Programmable Gate Arrays (FGPAs), one needs to effectively exploit the inherent parallelism in an algorithm. In the work we explore two approaches to FME algorithm parallelization in order to effectively increase the processing power of the computing hardware. The first method is referred to as vertical scaling and the second horizontal scaling. In total, we implemented six scaled FME designs on a Xilinx Virtex-5 FPGA. We found that our best scaled FME design exhibited a speedup of 8x over the horizontally scaled designs. Additionally, we conclude that scaling vertically within 4x4 pixel sub-block is more efficient than scaling horizontally across several sub-blocks. As a result we were able to achieve higher video resolutions at lower resource costs. In particular, it is shown that the best vertically scaled design can achieve 30 fps of QSXGA (2560x2048) video using 4 reference frames with only 25.5L LUTS and 28.7K registers.

A coarse-grained parallelization of genetic algorithms

Genetic algorithms are frequently used to solve optimization problems. However, the problems become increasingly complex and time consuming. One solution to speed up the genetic algorithm processing is to use parallelization. The proposed parallelization method is coarse-grained and employs two levels of parallelization: message passing with MPI and Single Instruction Multiple Threads with GPU. Experimental results show that the accuracy of the proposed approach is similar to the sequential genetic algorithm. Parallelization with coarse-grained method, however, can improve the processing and convergence speed of genetic algorithms.

AES Encryption Algorithm Parallelization in Order to Use Big Data Cloud Naser Attar, Hossein Deldari, Marzie Kalantari

Currently, standard encryption algorithms, such as AES, are used for encryption of data in cloud. As AES algorithm is a low-speed for serial, in addition to solving its low-speed, a Parallel Algorithms is introduced. Regarding the extent of cloud network, the most important feature of the proposed algorithm is its High speed and resistivity against the attacks. The algorithm is designed and implemented in java script in cloudsim environment. The results obtained from implementation of this algorithm in cloud simulating environment, are compared and evaluated relative to the other algorithms. Similar input was fed to the proposed and other algorithms. The proposed algorithm processed the data in 82 ms which is faster than the other algorithm.