Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool

2019 ◽  
pp. 52-63
Author(s):  
Luis Castano-Londono ◽  
Cristian Alzate Anzola ◽  
David Marquez-Viloria ◽  
Guillermo Gallo ◽  
Gustavo Osorio
Keyword(s):  
System On Chip ◽  
High Level Synthesis ◽  
Synthesis Tool ◽  
On Chip ◽  
High Level ◽  
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System on Chip Design with Vivado High-Level Synthesis Tool

2019 ◽  
Author(s):  
Bans Bilgili ◽  
Ceyhun Yamaneren ◽  
Kubilay Vatansever ◽  
Umut Coltu ◽  
Bema Ors
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System On Chip ◽  
High Level Synthesis ◽  
Chip Design ◽  
Synthesis Tool ◽  
On Chip ◽  
High Level

A Framework for High-Level Synthesis of System-on-Chip Designs

2006 ◽  
Author(s):  
J.E. Stine ◽  
J. Grad ◽  
I. Castellanos ◽  
J. Blank ◽  
V. Dave ◽  
...  
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System On Chip ◽  
High Level Synthesis ◽  
On Chip ◽  
High Level

scholarly journals System-on-Chip Design Using High-Level Synthesis Tools

2012 ◽  
Vol 03 (01) ◽  
pp. 1-9 ◽  
Author(s):  
Erdal Oruklu ◽  
Richard Hanley ◽  
Semih Aslan ◽  
Christophe Desmouliers ◽  
Fernando M. Vallina ◽  
...  
Keyword(s):  
System On Chip ◽  
High Level Synthesis ◽  
Chip Design ◽  
On Chip ◽  
High Level

High Level System-on-Chip Design using UML and SystemC

2007 ◽  
Author(s):  
Blanca Alicia Correa ◽  
Juan Fernando Eusse ◽  
Danny Munera ◽  
Jose Edinson Aedo ◽  
Juan Fernando Velez
Keyword(s):  
System On Chip ◽  
Level System ◽  
Chip Design ◽  
On Chip ◽  
High Level
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