High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Mapping Intimacies ◽

10.1007/978-981-10-1073-6 ◽

2018 ◽

Author(s):

Zheng Wang ◽

Anupam Chattopadhyay

Keyword(s):

System On Chip ◽

High Level Estimation ◽

On Chip ◽

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High Level System-on-Chip Design using UML and SystemC

Electronics, Robotics and Automotive Mechanics Conference (CERMA 2007) ◽

10.1109/cerma.2007.4367776 ◽

2007 ◽

Author(s):

Blanca Alicia Correa ◽

Juan Fernando Eusse ◽

Danny Munera ◽

Jose Edinson Aedo ◽

Juan Fernando Velez

Keyword(s):

System On Chip ◽

Level System ◽

Chip Design ◽

On Chip ◽

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High-level modeling and exploration of a powerline communication network based on System-on-Chip

Multi-objective Design Space Exploration of Multiprocessor SoC Architectures ◽

10.1007/978-1-4419-8837-9_7 ◽

2011 ◽

pp. 145-170

Author(s):

Marcos Martinez ◽

David Ferruz ◽

Hector Posadas ◽

Eugenio Villar

Keyword(s):

Communication Network ◽

System On Chip ◽

Powerline Communication ◽

High Level Modeling ◽

On Chip ◽

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A General Approach to High-Level Energy and Performance Estimation in System-on-Chip Architectures

Journal of Low Power Electronics ◽

10.1166/jolpe.2009.1037 ◽

2009 ◽

Vol 5 (3) ◽

pp. 373-384

Author(s):

Sandro Penolazzi ◽

Ahmed Hemani ◽

Luca Bolognino

Keyword(s):

System On Chip ◽

Performance Estimation ◽

Level Energy ◽

And Performance ◽

On Chip ◽

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Multidimensional representation of ultrasonic data processed by Reconfigurable Ultrasonic System-on-Chip using OpenCL high-level synthesis

2014 IEEE International Ultrasonics Symposium ◽

10.1109/ultsym.2014.0481 ◽

2014 ◽

Author(s):

Spenser Gilliland ◽

Clementine Boulet ◽

Thomas Gonnot ◽

Jafar Saniie

Keyword(s):

System On Chip ◽

High Level Synthesis ◽

On Chip ◽

Multidimensional Representation

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A Framework for High-Level Synthesis of System-on-Chip Designs

2005 IEEE International Conference on Microelectronic Systems Education (MSE'05) ◽

10.1109/mse.2005.8 ◽

2006 ◽

Author(s):

J.E. Stine ◽

J. Grad ◽

I. Castellanos ◽

J. Blank ◽

V. Dave ◽

...

Keyword(s):

System On Chip ◽

High Level Synthesis ◽

On Chip ◽

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Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool

Communications in Computer and Information Science - Applied Computer Sciences in Engineering ◽

10.1007/978-3-030-31019-6_5 ◽

2019 ◽

pp. 52-63

Author(s):

Luis Castano-Londono ◽

Cristian Alzate Anzola ◽

David Marquez-Viloria ◽

Guillermo Gallo ◽

Gustavo Osorio

Keyword(s):

System On Chip ◽

High Level Synthesis ◽

Synthesis Tool ◽

On Chip ◽

Algorithm Parallelization

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High-Level Crosstalk Defect Simulation Methodology for System-on-Chip Interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2004.833612 ◽

2004 ◽

Vol 23 (9) ◽

pp. 1355-1361 ◽

Author(s):

X. Bai ◽

S. Dey

Keyword(s):

System On Chip ◽

Simulation Methodology ◽

Defect Simulation ◽

On Chip ◽

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High-level system-on-chip simulator

2012 11th Conference of Open Innovations Association (FRUCT) ◽

10.23919/fruct.2012.8253117 ◽

2012 ◽

Author(s):

Aleksandr Orlov ◽

Alexey Syschikov

Keyword(s):

System On Chip ◽

Level System ◽

On Chip ◽

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High-level crosstalk defect simulation for system-on-chip interconnects

Proceedings 19th IEEE VLSI Test Symposium. VTS 2001 ◽

10.1109/vts.2001.923435 ◽

2002 ◽

Author(s):

Xiaoliang Bai ◽

S. Dey

Keyword(s):

System On Chip ◽

Defect Simulation ◽

On Chip ◽

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High-level Architecture of an IPSec-dedicated System on Chip

2007 Next Generation Internet Networks ◽

10.1109/ngi.2007.371211 ◽

2007 ◽

Author(s):

Alberto Ferrante ◽

Vincenzo Piuri

Keyword(s):

System On Chip ◽

High Level Architecture ◽

On Chip ◽

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